Stm32 Development notes 3 gpio

 

Gpio:

In the output mode of the I/O port, three output speeds (2 MHz, 10 MHz, and 50 MHz) are available ), this speed refers to the response speed of the I/O port drive circuit, rather than the output signal speed, the output signal speed is related to the Program (multiple output driving circuits with different response speeds are arranged in the output part of the chip at the I/O port, you can select a proper driver circuit as needed ). Select different output driver modules by selecting the speed to achieve optimal noise control and power consumption reduction. High-frequency driving circuit, high noise, when high output frequency is not required, please choose low-frequency driving circuit, this is very conducive to improve the system EMI performance. Of course, if you want to output a high-frequency signal, but choose a lower-frequency driver module, it is likely to get a distorted output signal.

The key is that the pin speed of gpio matches with the application (more than 10 times recommended ?). For example:

1.1.1 for serial ports, if the maximum baud rate is only 115.2 K, then the 2 m gpio pin speed is enough, both power saving and low noise.

1.1.2 for I2C interface, if the K Baud rate is used, if you want to keep the margin larger, then the 2 m gpio pin speed may not be enough, then you can choose 10 m gpio pin speed.

1.1.3 for the SPI interface, if the 18 m or 9 M Baud rate is used, the speed of the 10 m gpio pin is obviously insufficient, and the pin speed of 50 m gpio needs to be selected.

When the 1.2 gpio port is set as the input, the output drive circuit is disconnected from the port, so the output speed configuration is meaningless.

1.3 During the reset period and after the reset, the reuse function is not enabled, and the I/O port is configured as the float input mode.

1.4 all ports have external interrupt capabilities. To use external disconnection, the port must be configured in the input mode.

1.5 The configuration of the gpio port has the lock function. After the gpio port is configured, you can lock the configuration combination through the program until the next chip reset can be unlocked.

 

The resistance values of the internal pull-up and drop-down Resistors of stm32 are specified in the Data Manual, which is generally 30 ~ 50 k. The typical value is 40 K.

 

On the Internet, I can see some questions about resistance pull-up and drop-down. The pull-up and drop-down operations at the input end are very simple but also very important. The purpose of resistance is described below:

1. Resistance:
------- The connection resistance is used to prevent the input from being suspended.
------- Weaken the interference of external current on the chip
------- Protection of protection diodes in CMOS, the general current is not greater than 10mA
------- Pull-up, drop-down, and throttling
------- Changes the level of potential, often used in TTL-CMOS matching
------- Fixed status when pin is suspended
------- Increase the Driving Capability of high-level output.
------- Provide current for OC Gate

2. Definition:
Pull up:Connect to the power supply through a resistor.
Drop-down list:Through a resistor to the ground.
------- Pulling up is to embed uncertain signals through a resistor at a high level! The resistor can throttling at the same time! The same is true for the drop-down!
------- The upper PULL mode injects current into the device, and the drop-down mode is the output current.
------- Weak and strong only have different resistance values for the pull-up resistor. There is no strict distinction between them.
------- The capability of non-collector (or drain) open-circuit output circuits (such as common door circuits) to increase current and voltage is limited, the pull-up resistance function is mainly used for the output current channel of open collector output circuit.

3. Why do we need to use the pull resistance:
------- When used for single-key trigger, if the IC itself does not have an internal resistance, in order to make the single-key remain in the not triggered status or return to the original status after being triggered, A resistor must be connected to the outside of the IC.
------- The digital circuit has three states: high level, low level, and high resistance. In some applications, high resistance is not expected. You can use the pull-up or drop-down resistor to make it stable, depends on the design requirements!
------- I/O port is generally used, some can be set, some cannot be set, some are built-in, some need to be external, the output of I/O port is similar to the C of a transistor, when C is connected to the power supply through a resistor, the resistor becomes the upper C resistor, that is, if the port is normal, it is high, when C is connected to the ground through a resistor, the resistor is called a drop-down resistor, so that the port is usually low, for example: when a port connected with an active/standby resistor is set to an input state, its normal state is high, which is used to detect low-level input.
------- The pull-up resistor is used to provide current when the bus drive capability is insufficient. The pull current is generally used, and the drop-down resistance is used to absorb the current.

Generally, up/down pulling is useful in two ways:1) Improve the drive capability of the output signal; 2) determine the level of the input signal (to prevent interference ).

8051 of users know that the cpu I/O is usually blocked (up to 5 V), which is mainly used to improve the output drive capability. Because 8051 of the CPU is not a standard I/O port, the output is low and can absorb 20mA of the current at ordinary times, however, when the output is high, it is pulled up through a large internal resistor. When the output is high, the drive capability is poor. Therefore, the level output driving capability is improved through external pull-up.

Generally, each base pole of a transistor has two resistors. One Throttling is an upper or lower drop. The upper and lower latencies are mainly used to determine the level of the input signal. In fact, the goal is to prevent interference, because the input interface of the device generally has a large internal resistance and is vulnerable to interference. The uplink/downlink resistance reduces the input impedance and improves the anti-interference capability.

Generally, components do not need to use the input port to connect to the pull or drop-down resistance. Note that the output interface is not needed.

The input registers are still valid in the output mode, and the real bidirectional I/O function is implemented in the out-of-the-box configuration mode.

 

The floating input mode is used to test the analog voltage of the I/O port ???

 

Differences between the push-pull output and the open/Open output:

> Push-pull output: outputs high and low levels and connects to digital devices.

> Open-drain output: the output end is equivalent to the collector of the transistor. to obtain the High-level status, you need to pull up the resistance. it is suitable for current-type drive, and its ability to absorb current is relatively strong (generally less than 20 mA ).

//////////////////////////////////////// //////////////////////////////////////// //////////////////////////////////////// ////////////////// What are the characteristics of the open/drain output of the transistor, is it the same as pushing and pulling,
Problem:
Many chips have different power supply voltages, including 3.3v and 5.0 v. It is necessary to connect different ports of several kinds of IC together. Is it possible to connect them directly? In fact, the system is applied to I2C.
Answer:
1. Some 3.3v devices have 5 V compatibility and can be directly connected using this compatibility.
2. Apply a voltage converter. For example, tps76733 is a 5 V input, which is converted to 3.3 V and 1A output.
//////////////////////////////////////// //////////////////////////////////////// //////////////////////////////////////// ////////////////////

Characteristics and Application of Open leakage Channels

In circuit design, we often encounter the concepts of open drain and open collector. The "drain" mentioned in the so-called open-leakage circuit concept refers to the drain pole of the MOs. Similarly, the "set" in the open set circuit refers to the collector of the transistor. An on-line leakage circuit refers to a circuit with extremely high output of the MOs. In general, the pull-up resistance is added to the circuit with an external leakage pole. The complete open-leakage circuit should be composed of an Open-leakage device and an open-leakage pull-up resistor.

 

Circuit components have the following characteristics:
1. Use the drive capability of the external circuit to reduce the internal drive of the IC. When the internal MOS of the IC are turned on, the driving current is from the external VCC flowing through the R pull-up, the MOs to Gnd. The IC only needs a very low gate drive current. 1.
2. You can connect multiple pin pairs with open/missing output to an online line. Form a "logical" relationship. 1. When any one of pin_a, pin_ B, and pin_c gets low, the logic for online exposure is 0. This is also the principle that I2C, SMBus, and other bus determine the bus occupation status.
3. You can change the transmission level by changing the voltage of the pull-up power supply. 2. The logic level of the IC is determined by the power supply vcc1. the output height is determined by vcc2. In this way, we can use the low-level logic to control the output high-level logic.
4. when the Open-drain pin is not connected to the external pull-up resistor, it can only output a low level (therefore, for the P0 port of the classic 51 single-chip microcomputer, an external pull-up resistor is required for the input/output function, otherwise, the High-Level Logic cannot be output ).
5. The standard opening and dropping feet generally only have the output capability. Only by adding other judgment circuits can two-way input and output capabilities be achieved.

Note:
1. The principle of open-circuit and open-circuit is similar. In many applications, we use open-circuit to replace open-circuit. For example, an input pin must be driven by an open-leakage circuit. The common driving method is to use a transistor to form an open circuit to drive it, which is convenient and cost-effective. 3.
2. The R pull-up resistance determines the speed of the logical level conversion. The higher the resistance, the lower the speed and power consumption. And vice versa.

The push-pull output is generally called the push-pull output. It should be more suitable than the CMOS output in the CMOS circuit. The push-pull output capability in the CMOS circuit cannot be as large as the bipolar output capability. The output capability depends on the area of the N-tube p-tube output in the IC. Compared with the open-drain output, the level of push-pull is determined by the IC power supply, and logical operations cannot be performed simply. Push-pull is the most widely used output-level design method in the Current CMOS circuit.
Note the following when simulating the I2C interface at at91rm9200 gpio !!

1. What is OC and OD?

Open collector gate (open collector oC or open source OD)
Open-drain refers to the open-collector output, that is, the open-collector output in TTL. It is generally used for wire or, wire and some are also used for current driving.
Open-drain is for MOS tubes, and open-collector is for bipolar tubes, there is no difference in usage.
Open-drain circuit has the following features:
1. Use the drive capability of the external circuit to reduce the internal drive of the IC. Or drive load higher than the chip power supply voltage.
2. You can connect multiple pin pairs with open/missing output to an online line. A logical relationship is formed by means of an up-pull resistor without adding any device. This is also the principle that I2C, SMBus, and other bus determine the bus occupation status. If it is used as a totem output, it must be connected to the pulling resistance. When the capacitive load is connected, the descent delay is the transistor in the chip, which is the active drive and the speed is fast. The Descent delay is the passive external resistance, and the speed is slow. If the speed and high resistance are required, the power consumption will be high. Therefore, the choice of load resistance should take into account both power consumption and speed.
3. You can change the transmission level by changing the voltage of the pull-up power supply. For example, the TTL/CMOS level output can be provided by adding a pull-up resistor.
4. If the Open-drain pin is not connected to the external pull-up resistor, only the low level can be output. In general, open-drain is used to connect devices of different levels.
5. The normal CMOS output level is the upper and lower two tubes. Remove the above pipes as open-drain. This output has two main purposes: level conversion and line and.

6. Due to the open circuit of the lower-level circuit, the latter-level circuit must be connected to the upper-level resistance, and the power supply voltage of the upper-level resistance can determine the output level. In this way, you can convert any level.
7. the cables and functions are mainly used when multiple circuits are used to pull down the same signal. If the current circuit does not want to pull down, It outputs a high level because the pipe above open-drain is removed, high level is achieved by external pull-up resistance. (For a normal CMOS output level, if one output is high or the other is low, it is equal to a short circuit of the power supply .)

8. Open-drain provides a flexible output mode, but it also has its weakness, that is, the delay of the rising edge. Because the rising edge is charged by the external pull passive resistance, the latency is small when the resistance is selected, but the power consumption is large; otherwise, the delay is large and the power consumption is small. Therefore, if you have requirements for latency, we recommend that you use the descent edge output.

2. What is line or logic and line and logic?

On a single node (line), connect an upstream resistor to the Collector C or drain D of the power supply VCC or VDD and N or NMOS transistors, the emission pole E or source Pole s of these transistors are connected to the ground line. As long as there is a transistor saturated, this node (line) is pulled to the ground wire.
Because the base pole of these transistors is injected with current () or the gate is added with a high level (NMOS), the transistor will be saturated, so these base poles or gate nodes (lines) or non-Nor Logic. if this node is followed by an inverter, It is the or logic.

Note: For personal understanding, the cables and cables are connected to the power supply. (~ A )&(~ B) = ~ (A + B) the concept of this concept is easily understood by the formula;

If the drop-down resistor and PNP or PMOS tubes are used, they can form non-NAND logic, or convert and/or logic using a negative logical relationship.

Note: wire or drop-down resistor to the ground. (~ A) + (~ B) = ~ (AB );
These transistors are often open collector oC or source open circuit OD output of some logical circuits. this logic is usually called line and/line or logic. When you see that some chip's oC or OD output end are connected together and there is a pull-up resistor, this is the line or/line, but sometimes the pull-up resistance is done in the input of the chip.
By the way, it is suggested that the output end of the OC or OD chip cannot be connected together. The two-way output end of the bus can be managed together, and only one output can be made at the same time, other high-impedance states can only be input.

3. What is a push-pull structure?
Generally, two transistors are controlled by two complementary signals, which always end when one transistor is turned on. the OC (open collector) door circuit must be used to achieve the line and the need. if there are two transistors in the output level, they are always in one conduction and one cutoff state, that is, two three-level tubes are pushed and connected. Such a circuit structure is called a push-pull circuit or a totem-pole) output Circuit (unfortunately, the figure cannot be attached ). When the output power is low, that is, when the lower-level load gate inputs low, the output current is when the lower-level load gate inputs T4; when the output power is high, that is, when the lower-level load gate inputs High, the current at the output end will be pulled from the lower-level power supply through T3 and D1. In this way, the T3 and T4 channels work in turn to reduce power consumption and improve the affordability of each pipe. Regardless of the path, the on-resistance of the pipe is very small, so that the RC constant is very small, and the transformation speed is very fast. Therefore, the push-pull output level not only improves the load capacity of the circuit, but also increases the switching speed. For your reference.
The push-pull circuit is a three-circuit transistor or transistor with the same parameters. It exists in the circuit in the push-pull mode. It is responsible for waveform amplification tasks of plus or minus half weeks. When the circuit works, the two symmetric power switches have only one on-going switch at a time, so the low conduction loss is highly efficient.

The output can either inject current to the load or extract current from the load.