STM32 in-store distribution and bus

1. Bus system structure

The system consists of a matrix consisting of multiple interconnected 32-bit AHB buses

• 8 Main bus

    –CORTEX-M4 with FPU core I-bus, D-bus and S-bus    –dma1 memory bus –dma2    memory bus    –dma2 Peripheral bus
   
    –ethernet DMA bus    – USB OTG HS DMA Bus
   

• 7 from the bus:

    –internal Flash memory ICode bus    –internal Flash memory DCode bus    –main Internal SRAM1 (in. KB)    –auxili ary internal SRAM2 (KB)    –AHB1 peripherals including AHB to APB bridges and APB Peripherals    –AHB2 Peripheral S    –FSMC

The bus matrix also provides master-to-slave access that enables concurrent access and can work efficiently even when multiple high-speed peripherals work simultaneously. the 64Kbyte CCM (core coupled memory) data RAM is not part of the bus matrix and is accessible only through the CPU.

Bus type

• I-bus

  The bus connects the command bus with the FPU's cortex-m4 core to the Busmatrix. The bus is used by the kernel to take command operations. The control target of the bus is a piece of memory that includes code (internal Flash Memory/sram or external memories through the FSMC/FMC).

• D-bus

  The bus connects the data bus with the FPU's cortex-m4 core to the 64Kbyte CCM data RAM to the Busmatrix. The bus is used by the kernel to download code and debug. The control target of the bus is a piece of memory that includes code or data (internal Flash memory or external memories through the FSMC/FMC).

• S-bus

  The bus connects the system bus with the FPU's cortex-m4 core to the Busmatrix. The bus is used to access data loaded into the SRAM or peripherals. Instructions may also be obtained via the bus (no icode is efficient). The control objectives of the bus are: internal SRAM1, SRAM2 and SRAM3, AHB1 peripherals (including APB peripherals), AHB2 peripherals and external memory through FSMC/FMC

• Busmatrix

  Busmatrix manages access arbitration between the main bus. Arbitration using loop algorithm

Bus structure diagram:

2. Memory distribution

• The programming Space (code space), the data space, the register, and the I/O ports are organized in the same linear 4Gb space. All data is stored in small end
• Addressable memory space is divided into 8 blocks, each of which includes 512MB
• All space that is not allocated to on-chip memory or on-chip peripherals is "reserved"

Embedded SRAM

• The STM32F407ZG is configured with a 4 Kbytes backup sram,192 Kbytes system SRAM.
• Embedded SRAM can be accessed in bytes, half-word, word, and can be accessed at CPU speed without waiting, embedded SRAM is divided into the following 3 blocks:
  
  • SRAM1 and SRAM2 map to 0x2000 0000 addresses and can be accessed by all AHB buses.
  • SRAM3 (only Stm32f42xxx and STM32F43XXX series available) map to 0x2002 0000 address and can be accessed by all AHB buses
  • CCM (core coupled memory) maps to 0x1000 0000 addresses only through D-bus CPU access

Bit band operation

Two bit-band operation fields and corresponding bit-band alias domains are available in STM32

bit band operation Field	bit with alias Domain
SRAM low 1M bytes: 0x2000 0000~0x200f FFFF	0x2200 0000~0x23ff FFFC
Low 1M bytes for peripherals: 0x4000 0000~0x400f FFFF	0x4200 0000~0x43ff FFFC

Bit band Operation Formula:

bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number × 4)

Example:

0x220060080x22000000 + (0x300*32) + (2*4)/* 对0x22006008的读写就实现了对0x2000 0300处第2个bit的读写 *//* 同理，若要对0x40000000地址块进行位操作，需要把上面式子右边的0x22000000换成0x42000000 */

In the future we want to directly manipulate a bit of a register, only need to find the corresponding alias address, and then read and write to the alias address to achieve this bit read and write. If you want to do this, you only need to define macros, such as the following:

#define REGISTER_BIT_BAND(ofs, bit_num) (052(*((volatile unsigned int *)REGISTER_BIT_BAND(ofs, bit_num)) = stat)//上面两个宏可以实现对寄存器位带域的操作

3, start the configuration start mode

Boot mode selection pins		Boot Mode	aliasing
BOOT1	BOOT0
X	0	Main Flash Memory	Main Flash Memory is selected as the boot space
0	1	System Memory	System memory is selected as the boot space
1	1	Embedded SRAM	Embedded SRAM is selected as the boot space

My board startup is in main flash memory, by the front of the ARM compiler tool section can know the code from the 0x08000000 start to run, this is also by the distributed loading file specified, is also the board above main flash actual address

Physical Address Remapping

• The following memory spaces can be re-mapped:

- Main Flash memory- System memory- Embedded SRAM1 (112 KB)- FSMC bank 1 (NOR/PSRAM 1 and 2)

The mapping table is

The memory block mapped to the 0x00000000 address can be determined by the low two bits of the SYSCFG controller's (SYSCFG_MEMRMP) register, as shown in the following table

bit1	bit0	Memory Selected
0	0	Main Flash memory mapped at 0x0000 0000
0	1	System Flash memory mapped at 0x0000 0000
1	0	FSMC Bank1 (Nor/psram 1 and 2) mapped at 0x0000 0000
1	1	Embedded SRAM (SRAM1) mapped at 0x0000 0000 from the table

As you can see, flash memory is remapped to the beginning of the 0 address at the start of main Flash, 1MB, but my board is still running code from the 0x08000000 address, and now It can be seen from the data in the table that it is possible to run from a 0 address, possibly to accommodate different startup methods, so that the system code is run from the 0x08000000 address. If you want to run the code in Flash memory from somewhere else, simply jump to the 0x08000000 address to run the code in the same way that it is remapped to the beginning of the 0 address space code snippet and a jump statement.

4. Embedded Flash Memory Interface features:

• Flash Memory Read operation
• Flash Memory Programming/erase operation
• Read/write protection
• Pre-fetching of instructions
• The I-code has 64 128-bit wide quick access lines
• The I-code has 8 128-bit wide quick access lines

Flash memory Features:

• 1M byte capacity
• 128 bits of read data bit width
• Supports Byte, Half-word, Word and double word writes
• Supports sector and block erase
• Support for Memory organization
  
  • Flash memory can be organized in the following way:
    
    • –main memory is divided into 4 kbytes size sectors, 1 x kbytes size sectors, and 7 Kbytes size sectors
    • – Different boot devices correspond to the corresponding system memory
    • –512 OTP (Disposable programming) bytes
    • – optional configuration read/write protection
• Low Battery mode

Memory Distribution Map

Additional Clock additions:

VOS is set in the bit15 bit of the PWR_CR register

When VOS = ' 0 ', the FHCLK is 144 MHz maximum.
When VOS = ' 1 ', the FHCLK is 168 MHz maximum.

Wait period

STM32 in-store distribution and bus