STM32------independent watchdog (IWDG) and form watchdog (WWDG)

A Frontier Waste language:

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Second straight to the point:

Below the bottom, the STM32 used in work requires the use of watchdog technology:

Watchdog popular explanation:

Single-chip microcomputer system in the external interference will appear in the program to run the phenomenon of flying caused by the death cycle, watchdog circuit is to avoid the occurrence of this situation. The function of the watchdog is to realize the automatic reset of the processor (sending the reset signal) by not receiving the dog feed signal (which means that the MCU is already dead) within a certain time (through the timer counter).

Three Lushan faces:

STM32 chip A total of two watchdog, one is independent watchdog (IWDG), the other is the form watchdog (WWDG)

① first talk about the independent watchdog:

The independent watchdog of the STM32 is driven by an internal dedicated 40Khz low-speed clock, and even if the master clock fails, it still
Effective. It's important to note that the independent watchdog clock is an internal RC clock, so it's not exactly 40Khz, but
A changeable clock between the 30~60khz, just when we estimate, at 40Khz frequency to calculate, see
And the time requirements are not very accurate, so the clock is a bit biased, are acceptable.

Configuration work code for the standalone watchdog:

1 voidiwdg_init (U8 prer,u16 rlr)2 {3Iwdg_writeaccesscmd (iwdg_writeaccess_enable);//① enable to register I write operation4Iwdg_setprescaler (Prer);//② Setting the IWDG prescaler value: Setting the IWDG prescaler value5Iwdg_setreload (RLR);//② Setting IWDG Reload value6Iwdg_reloadcounter ();//③ Reload IWDG counter according to the value of IWDG reload register7Iwdg_enable ();//④ Enable IWDG8 }9 //Hey, independent watchdog .Ten voidIwdg_feed (void) One { AIwdg_reloadcounter ();//Reload -}

Main Logic Area code:

1 delay_init ();//initialization of the delay function2Nvic_configuration ();//set NVIC Interrupt grouping 2:2-bit preemption priority, 2-bit response priority3Key_init ();//Key Initialization4Iwdg_init (4,625);//with a crossover number of 64, an overload value of 625 and an overflow time of 1s5  while(1)6 {7     if(Key_scan (0)==key_up)8     {9Iwdg_feed ();//If you press the button, feed the dog.Ten     } OneDelay_ms (Ten); A}

The function of the program is to open the watchdog by pressing the button and perform the corresponding operation when the watchdog is triggered.

② look at the form watchdog again.

Window watchdog (WWDG) is often used to monitor applications caused by external interference or unforeseen logic conditions
A software failure caused by a deviation from the normal running sequence. Unless the value of the decrement counter is in the T6 bit (sixth bit of WWDG->CR)
becomes 0 before being refreshed, the watchdog circuit generates an MCU reset when it reaches the preset time period. In descending count
Before the window configuration register (WWDG->CFR) value is reached, if the 7-bit decrement counter value (in the control register)
is refreshed, then an MCU reset is also generated. This indicates that the decrement counter needs to be brushed in a limited time window
New.

Watchdog Time Calculation formula:

The timeout formula for window watchdog is as follows:
Twwdg= (4096X2^WDGTBX (t[5:0]+1))/fpclk1;
which
TWWDG:WWDG time-out (in MS)
FPCLK1:APB1 clock frequency (in Khz)
The prescaler coefficient of WDGTB:WWDG
T[5:0]: Window watchdog counter low 6 bits

1 voidwwdg_init (U8 tr,u8 wr,u32 fprer)2 {3Rcc_apb1periphclockcmd (RCC_APB1PERIPH_WWDG, ENABLE);//WWDG Clock Enable4wwdg_cnt=tr&wwdg_cnt;//initializes the wwdg_cnt.5Wwdg_setprescaler (Fprer);//Setting the IWDG prescaler value6Wwdg_setwindowvalue (WR);//Setting window Values7 wwdg_enable (wwdg_cnt);8 　　　　 //enable watchdog, set counter9Wwdg_clearflag ();//Clear early Wakeup interrupt flag bitTenWwdg_nvic_init ();//Initialize window watchdog NVIC OneWwdg_enableit ();//turn on window watchdog interrupt A } - //resetting the value of the WWDG counter - voidWwdg_set_counter (U8 cnt) the { -Wwdg_enable (CNT);//enable watchdog, set counter. - } - //window watchdog interrupt Service program + voidWwdg_nvic_init () - { + nvic_inittypedef nvic_initstructure; ANvic_initstructure.nvic_irqchannel = WWDG_IRQN;//WWDG Interrupt atNvic_initstructure.nvic_irqchannelpreemptionpriority =2;//preemption 2 Sub-priority 3 Group 2 -Nvic_initstructure.nvic_irqchannelsubpriority =3;//preemption 2, sub-priority 3, group 2 -Nvic_init (&nvic_initstructure);//NVIC Initialization - } - voidWwdg_irqhandler (void) - { in  　　　　 Wwdg_setcounter (wwdg_cnt); -  　　　　 //when this sentence is banned, the window watchdog will produce a reset to Wwdg_clearflag (); +  　　　　 //Clear early Wakeup interrupt flag bit -led1=!LED1; the //LED Status Flip *}

Main Logic Area code:

1 intMainvoid)2 {3Delay_init ();//initialization of the delay function4Nvic_configuration ();//set NVIC interrupt grouping 25 usart1_init (); serial 1 initialization6Led_init ();//LED Initialization7Key_init ();//Key Initialization8led0=0;9Delay_ms ( -);TenWwdg_init (0X7F,0x5f, wwdg_prescaler_8);//The counter value is 7f, the window register is 5f,//Divide number is 8 One      while(1) A     { -led0=1; -     } the}

Function:

Indicates whether the initialization is being initiated by LED0 (DS0). The LED1 (DS1) is used to indicate whether the
Broken. Let's make the LED0 light 300ms and then turn it off to determine if a reset has occurred. In the initialization of the WWDG
After we return to the dead loop, turn off the LED1 and wait for the watchdog to interrupt the trigger/reset.

Four generalities:

Let's analyze the difference between the independent watchdog (IWDG) and the form watchdog (WWDG):

(1) Independent watchdog without interruption, window watchdog has interrupt (2) Independent watchdog has hardware software points, Windows watchdog only software control (3) independent watchdog only lower limit, window watchdog and Upper limit (4) Independent watchdog is 12-bit descending. Window watchdog is a 7-bit descending (5) Independent watchdog is used for the internal 40KHZ RC oscillator, Windows watchdog is used by the system clock APB1ENRend!

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STM32------Independent watchdog (IWDG) and form watchdog (WWDG)