STM32 Learning--timer (basic timer)

1. Function and principle

The basic timers TIM6 and TIM7 each contain a 16-bit automatic load counter, which is driven by the respective programmable prescaler. They can provide a time base as a general-purpose timer, especially for a digital-to-analog converter (DAC). In fact, they connect directly to the DAC inside the chip and drive the DAC directly through the trigger output. These 2 timers are independent of each other and do not share any resources.

The graph shows that its clock source can only be derived from PCLK1, when the PCLK1 prescaler coefficient is 1 o'clock timclk =pclk1, otherwise timclk =2*pclk1. The drive clock of the counter = TIMCLK/PSC.

The counter for the base timer is an accumulation counter, and the counter value (CNT) is incremented from 0 to the auto load value (ARR), resulting in an overflow event that causes an update event for each overflow event, resulting in a corresponding interrupt when the interrupt is enabled.

A more specific point is about the runtime modifying the values of ARR and PSC. This requires understanding the shadow registers, arr and PSC have two registers, one holds the value we write, the shadow register is actually the value at runtime.
The shadow registers of ARR are controlled by the Arpe bit in the _CR1 to enable. Arpe the pre-loaded value is transferred to the Shadow register immediately, and the CNT counts to the new preload value to generate an overflow event; Arpe 0 o'clock preload values are transferred to the shadow register after an update event, and CNT counts to the original preload before updating the shadow register. The next count will be counted as the new preload value.
The shadow registers of the PSC will only be transferred to the shadow register after an update event.
There are two more points about update events:
The URS bit in _CR1 can select the request source for the Uev event, 0: If interrupt or DMA is enabled, any of the following events can produce an update interrupt or DMA Request: Counter overflow, set UG bit, update generated from the mode controller (this does not seem to be the case). For 1 o'clock, if interrupt or DMA is enabled, only a counter overflow can generate an update interrupt or DMA request.
The Udis bit disables the update, which is enabled for the 0 O'Clock update event, and does not produce an update event (Uev) at 1, and the shadow register retains its contents (ARR, PSC). However, if the UG bit is set, the counter and Prescaler will be reinitialized.

Single pulse mode: OPM selected in _CR1, 1 o'clock, the counter stops counting (clears the CEN bit) when the next update event occurs. 2. Register

TIMX_CR1: In addition to the previous introduction of Arpe, OPM, URS, Udis, only CEN, is to enable the timer.
TIMX_CR2: Set main Mode select MMS, since the clock can only be derived from PCLK1, so the individual feels it cannot work in slave mode. But you can work in main mode.

000: Reset – Use the UG bit of the TIMX_EGR register as the trigger output (Trgo).
001: Enable the –> counter enable signal cnt_en to be used as the trigger output (Trgo).
010: Update – Update event is used as trigger output (Trgo).

Timx_dier: Use only 2 bits, respectively enable DMA and enable interrupt.
TIMX_SR: Only 1 bits are used to identify the update interrupt.
Timx_egr: Only 1 bits, UG: Generate Update events, set 1 o'clock, re-initialize the timer counter and generate updates to the register. Note: The Prescaler is also cleared (but the prescaler coefficient is constant).
Timx_cnt, TIMX_PSC, Timx_arr: Count value, divide factor, preload value, respectively. 3. How to use

Basic methods of Use:
①timx clock Enable.
② sets the values of Timx_arr and TIMX_PSC.
③ settings timx_dier allow update interrupts.
④ allows Timx to work and start counting.
⑤TIMX Interrupt grouping settings.
⑥ writes the interrupt service function, which should, after processing the interrupt, write 0 to the lowest bit of the TIMX_SR to clear the interrupt flag.