STM32 NVIC (interrupt vector, priority) brief

first, the background needs to use the STM32 can for communication, after a series of configurations, has been able to send and receive, but also left a can communication error processing. The error interrupt enable register is configured to be enabled, and after an error, it cannot be entered"Can1_sce_irqhandler"interrupts. (The way to make the can communication error is very simple, will"Can_h"And"can_l"direct short, and then let it send the data, normally, it will trigger an error interrupt, send error register will be added instantly to" -", if you continue to send, every time, send error counter will +8until 256, then the can node goes offline, i.e."Bus off"status). Step by step to find out ,"can1_sce_irqn"The M3 kernel interrupt is not on, that is, the Nvic related configuration. For Nvic really do not understand, fortunately there is an old driver Zodong-although he still on this title is refused:)-with Zodong learned a lot, thank you very much. Second, the text for Nvic (Nested vectored Interrupt Controller), Chinese is generally translated into nested vector interrupt Controller,
It is the M3 kernel hierarchy concept and the related register configuration needs to be used to Cotex-M3 Data Sheet, ST's user manual involves less, fortunately there are St's libraries
function, this time do not delve into Nvic, only the concept of Nvic and its corresponding library function use to do a brief description. STM32 is based on CotexMcu,cotex-of the-M3 kernelM3 has two priority concepts:--->preemption Priority (primary priority)--->Response Priority (sub-priority) its actual hierarchy concepts such as:

, the task of preemption with low priority is interrupted when the high priority tasks occur, that is, the so-called interrupt nesting. For example:--->preemption Priority n Interrupt task is running, at this time, preemption priority is 2 interrupt generation, the MCU will be steals priority N of the task interrupt, first respond to the task of performing an interrupt priority of 2, after the task is completed, and then to complete the preemption Priority N task. --->if an interrupt with a preemption priority of 2 is running and a new preemption priority of 2 is generated, the newly generated interrupt waits for the current task to complete before performing a new interrupt. --->in the case of preemption priority, interrupts with the same sub-priority are generated at the same time, the interrupt task is performed according to the order of the interrupt vector table. The above tasks are all done by CotexThe-M3 core Nvic (Interrupt Controller) is completed. In the interrupt controller, the cotex-the M3 defines a 1-byte (8-bit) register to define preemption priority and response priority. It is defined as follows:--->up to 1 bits are used to specify preemption priority, with a minimum of 7 bits to specify the response priority--->up to 2 bits are used to specify preemption priority, with a minimum of 6 bits to specify the response priority--->up to 3 bits are used to specify preemption priority, with a minimum of 5 bits to specify the response priority--->up to 4 bits are used to specify preemption priority, with a minimum of 4 bits to specify the response priority--->up to 5 bits are used to specify preemption priority, with a minimum of 3 bits to specify the response priority--->up to 6 bits are used to specify preemption priority, with a minimum of 2 bits to specify the response priority--->up to 7 bits are used to specify preemption priority, with a minimum of 1 bits to specify the priority of the response such a large string, beginning I also very confused, after the left old driver guidance, only to understand. As previously stated, this register has a total of 8 bits, if the maximum 1 bits for the specified preemption priority, the lowest 7 bits for the specified response priority, which means that preemption priority is only 2^1= 2, each preemption priority corresponding to the corresponding priority level has 2^7= -A.        The others are and so on. STM32 does not use all 8 bits, but only 4 bits, so it defines 5 priority groupings, as follows:--->#defineNvic_prioritygroup_0 ((uint32_t) 0x700)/*0 Bits for pre-emption priority * 4 bits for subpriority*/        //with 2^0 = 1 preemption priority, 2^4 = 16 Response Priority--->#defineNvic_prioritygroup_1 ((uint32_t) 0x600)/*1 bits for pre-emption priority * 3 bits for subpriority*/        //with 2^1 = 2 preemption priority, 2^3 = 8 Response Priority--->#defineNvic_prioritygroup_2 ((uint32_t) 0x500)/*2 bits for pre-emption priority * 2 bits for subpriority*/        //with 2^2 = 4 preemption priority, 2^2 = 4 Response Priority--->#defineNvic_prioritygroup_3 ((uint32_t) 0x400)/*3 bits for pre-emption priority * 1 bits for subpriority*/        //with 2^3 = 8 preemption priority, 2^1 = 2 Response Priority--->#defineNvic_prioritygroup_4 ((uint32_t) 0x300)/*4 bits for pre-emption priority * 0 bits for subpriority*/        //with 2^4 = 16 preemption priority, 2^0 = 1 Response PriorityFirst, ST provides library functions"void Nvic_prioritygroupconfig (uint32_t nvic_prioritygroup)"to set preemption priority and Response priority group types, Parameters"Nvic_prioritygroup"the 5 macro definitions mentioned above. The St also provides library functions"void Nvic_init (nvic_inittypedef*nvic_initstruct)", the library function is based on the structure"nvic_initstruct"The contents of the Nvic complete the configuration, which is defined as follows: TypeDefstruct    {        //define which interrupts (e.g. "usart1_irqn", "usb_lp_can1_rx0_irqn", etc.)uint8_t Nvic_irqchannel; //What is the preemption priority for this interrupt?uint8_t nvic_irqchannelpreemptionpriority; //What is the response priority for this interrupt?uint8_t nvic_irqchannelsubpriority; //the value represents whether the setting is in effect (ENABLE, DISABLE)functionalstate Nvic_irqchannelcmd;    } nvic_inittypedef; Record time: September 10, 2016 record location: Shenzhen wz

STM32 NVIC (interrupt vector, priority) brief