Stm32 SPI NSS PIN usage configuration

NSS PIN for STM
First we say that the pin has two levels to note, one is the external level connected to the NSS pin, and the other is the internal level of the NSS pin.
Then we know that at the time of SPI Communication, master must be able to communicate at the internal level of the NSS pin before it is high, and the slaver can communicate at low levels at the internal level of the NSS pin. This is a precondition.
We know that there are two ways to manage NSS pin levels, one is software management and hardware management. However, when the hardware is managed (ssm=0), the internal level of the NSS pins is determined by the external level of the NSS connection, i.e. the outside is high, and the internal level of the NSS pin is high. If you want to work in this mode, then the NSS pin of master must be connected high, and the slaver must be connected to a low level (general ground). The Software Management mode (Ssm=1) uses the SSI bit to determine whether the internal level is high or low. The ssi=1 is the internal level of the NSS pin is high, this time is not related to the level of the external input, STM set the NSS PIN software management is to be able to empty the NSS pin, like the normal IO pin application. If you work in this mode, Master's ssm=1,ssi=1,slaver is ssm=1,ssi=0. Also fast is the master configured as a software management, slaver hardware management configuration, communication when Master Ssm=1,ssi=1;slaver the NSS pin to any of the master's IO pins, the external level of the NSS pin must be low when communicating.
Finally, if the STM communicates with other IC chips through the SPI, it is generally possible to configure: STM as Master can be configured as Software Management mode (Ssm=1), at which the NSS pin potential is determined by the SSI bit and the STM communication is SSI must be 1 The CS pin of the IC chip can be connected to any IO pin (including the NSS pin) for communication control.