STM32 TAMPER-RTC pin as tamper use [turn]

Question one:

When the signal on the tamper pin changes from 0 to 1 or from 1 to 0 (depending on the tpal bit of the backup control register BKP_CR), an intrusion detection event is generated. The intrusion detection event clears all data backup register contents.
However, in order to avoid loss of intrusion, the intrusion detection signal is the logic of the edge detection signal and the intrusion detection allow bit, which can also be detected before intrusion detection pins are allowed to occur before the intrusion event.
When tpal=0: If the pin is already high before starting the Intrusion detection tamper pin (by setting the TPE bit), an additional intrusion event is generated once intrusion detection is initiated (although no rising edge occurs after TPE position 1).
When tpal=1: If the pin is already low before starting the intrusion detection pin tamper (by setting the TPE bit), an additional intrusion event is generated once the intrusion detection function is initiated (although no lower edge occurs after TPE position 1).
After an intrusion event is detected and cleared, the intrusion detection pin tamper should be disabled. Then, re-start the intrusion detection function with the TPE bit before writing the backup data register again. This prevents the software from writing to the backup data register when there are still intrusion events on the intrusion detection pin. This is equivalent to the intrusion pin tamper input level detection.

Note: Intrusion detection is still valid when the VDD power supply is disconnected. To avoid unnecessary reset data backup registers, the tamper pin should be connected to the correct level on the off-chip.

Answer: "Note: The intrusion detection function is still valid when the VDD power supply is disconnected. To avoid unnecessary reset data backup registers, the tamper pin should be connected to the correct level on the off-chip. "This sentence not too tangled, this is the hardware to do the work, do not be dead, if you want to understand can communicate with hardware engineers." The responsibility of our software is to set the correct temper level signal here.

When tpal=0, we should pull the temper pin low.

When tpal=1, we should pull the temper pin high. (In fact, the chip design is observed, thetemper pin is the high level by default)

Question two:

"After an intrusion event is detected and cleared, the intrusion detection pin tamper should be banned. Then, re-start the intrusion detection function with the TPE bit before writing the backup data register again. This prevents the software from writing to the backup data register when there are still intrusion events on the intrusion detection pin. This is equivalent to the level detection of the intrusion pin tamper. ”
Answer: The main is the red Word part, why we do not let others write and disable tamper pin, in fact, we do not let others write, is good for the user, can not let others suffer. Because if you put the signal in, the last time you have closed the interrupt, when there is an intrusion, only the intrusion event flag is changed by the hardware, and not into the interrupt processing subroutine, so that the backup data register can not be reset, then the contents of the backup data register may be stolen, So we're going to prohibit tamper pin.
In this case, there is a problem, intrusion permit, when the configuration of the interrupt when the loss of energy, then the intrusion signal, then the data register is not the content of the automatic purge? Experiments need to be done to further verify.

Reprinted from: http://blog.chinaunix.net/uid-26285146-id-3074111.html

STM32 TAMPER-RTC pin as tamper use [turn]