STM32 timer:base Timer, Input Capture, PWM, Output Compare

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An example of a basic timer was illustrated in Figure 10.1.

This timer had four components–a controllers, a Prescaler (PSC), an "auto-reload" register (ARR) and a counter (CNT).

The function of the prescaler is to divide a reference clock to lower frequency.

The STM32 timers has 16-bit prescaler registers and can divide the reference clock by any value 1..65535.

For example, the 24Mhz system clock of the STM32 VL Discovery

Could is used to generate a 1 Mhz count frequency with a prescaler of (0..23 = = values). T

He counter register can configured to count up, down, or Up/down and to is reloaded from the auto reload register

Whenever it wraps around (an "update event") or to the stop when it wraps around.

The basic timer generates an output event (Tgro) which can be configured

To occur in an update event or, the counter is enabled (for example on a GPIO input).

To understand, the three counter modes consider Figure 10.2.

In these examples, we assume a prescaler of 1 (counter clock is half the internal clock), and a auto reload value of 3.

Notice in ' Up ' mode, the counter increments from 0 through 3 (ARR) and then was reset to 0.

When the reset occurs, a "update event" is generated.

This update event is tied to Trgo, or in the more complex timers with capture/compare channels

It may have additional effects (described below).

Similarly, in ' Down ' mode, the counter decrements from 3 through 0 and then was reset to 3 (ARR).

In-down mode, an update "event" (Uev) was generated when the counter was reset to ARR.

Finally, in Up/down mode, the counter increments to ARR, then decrements to 0, and repeats.

A Uev is generated before each reversal with the effect so the period in Up/down mode

is one shorter than in either up or down mode.

Many timers extend this basic module with the addition of counter channels such as the one illustrated in Figure 10.3.

The "X" refers to the channel number–frequently, timers support multiple channels.

With this modest additional hardware, an output can be generated whenever the count register reaches a specific value< /c0>

Or the counter register can captured when a specific input event occurs (possibly a prescaled input clock).

An important use of counter channels is the generation of precisely timed pulses.

There is variations of this use– "one-pulse" pulses,

In which a single pulse are generated, and pulse width modulation, in which a series of pulses are generated with the Counte R Uev period.

The pulse width is controlled by the Capture/compare Register (CCR).

For example, the channel output (OCXREF) could tied to whether the CNT register was greater (or less) than the Compare regist Er.

In Figure 10.4 We illustrate the use of both channels for One-pulse and PWM outputs.

Here we assume the ARR are 7 and the CCR is 3.

In PWM mode, ARR controls the period, and CCR controls the pulse width (and hence the duty cycle).

In One-pulse mode, the pulse begins CCR cycles after an initial trigger event, and has a width of ARR-CRR.

It is possible to use multiple channels to create a set of synchronized, pulses beginning at precise delays from each othe R.

A Timer channel may also is used to measure pulse widths–in effect decoding PWM signals.

There is many other configuration options for the STM32 timers including mechanisms

To synchronize multiple timers both to all other and to external signals.

In the remainder of this chapter we consider both timer applications including PWM output (section 10.1),

Input pulse measurement (Section 10.2).

In Chapter the We show how to use a timer to control DMA transfers for a audio player and

In Chapter, we use a timer to sample and analog input at regular intervals.

STM32 timer:base Timer, Input Capture, PWM, Output Compare