STM32 USART serial Communication [Operation Register + library function]__stm32

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Although the serial communication in today's computer use fewer and less, because of its communication rate, distance has not adapted to the requirements of the PC, replaced by a USB port.    But in the embedded field, Usart is still widely used. Stm32 can provide a maximum of 5-way serial port, there is a fractional baud rate generator, support synchronous single line communication and Half-duplex single line communication, with DMA and so on.    When using Usart, the stm32 I/O port is connected by the RS232 level conversion circuit and the serial port of the computer.   The use of serial port only need to start serial clock, set the corresponding I/O port mode, configure baud rate, data bit length, parity bit information can be used. I use three ways to use serial communication, can only open one: Usart by using the printf () function to send information, Usart and host computer communication, receive the data after the original data output; Usart send the data voluntarily.Operation Registers      The reset of the serial port is through the configuration of the 14th bit of the APB2RSTR register, when the peripheral fault, can reset register reset, when the system initialization, will perform the reset operation.       Serial port baud rate setting is on the USART_BRR register, in fact this register is configured with the baud ratio of the frequency of the trigger factor, baud rate is a second pass of the character, and the baud ratio is a second pass the number of bits, So set the baud rate need to pass through a section of algorithm processing, to get a specific clock, to achieve this baud rate, the clock frequency division value.       Serial control registers have 3 usart_cr1~3, commonly used is USART_CR1, you can describe as follows:    ue:usart enable (USART enable)     M: Word length   This bit defines the length of the data word,  0: A starting bit, 8 data bits, n stop bits, 1: A start bit, 9 data bits, n stop bits. n is set by USART_CR2.    wake: Wake-up (Wakeup method)  0: Wake by Idle bus;  1: awakened by address tag.    PCE: Inspection control Enabling (Parity controls enable)    ps: Checksum selection (Parity selection)  0: parity; 1: Odd checksum.    PEIE:PE Interrupt enable (PE interrupt enable)   txeie: Send buffer air break enable (Txe interrupt enable)    Tcie: Send complete interrupt enable (transmission complete interrupt enable)   rxneie: Receive buffer not air break enable (Rxne interrupt enable)  & Nbsp;idleie:idle interrupt enable (IDLE interrupt enable)  0: Prohibit interrupt generation,  1: Usart_sr interrupts when IDLE in Usart is ' 1 '.  te: Send to enable (transmitter Enable)  re: Receive enable (Receiver enable)  rwu: Receive wake-up (Receiver wakeup)  0: The receiver is in normal working mode;  1: The receiver is in silent mode. Note: 1. Before placing Usart in silent mode (setting the RWU bit), Usart must have received a byte of data first. Otherwise, it cannot be awakened by idle bus detection in silent mode. 2. When configured as an address mark detection wake-up (Wake bit =1), the RWU bit cannot be modified with software when Rxne bit is set.  SBK: Send a disconnected frame (send break)     Send and receive data is implemented in USART_DR, this is a dual register, including TDR and RDR, when the register to write data, the serial port will automatically send data; when data is received , which is also present in the register, can be read directly. The register is only 9 digits valid (8:0), and the other bits are reserved.

The serial state is read by the State Register USART_SR, you describe as follows: Txe: Send data register empty (transmit data register empty) when the data in the TDR register is transferred to the shift register by hardware, the bit is placed by the hardware. If the Txeie in the USART_CR1 register is 1, an interrupt is generated.         For Usart_dr writes, the bit is zeroed out.     0: The data has not been transferred to the shift register; 1: The data has been transferred to the shift register. TC: Send complete (transmission complete) when a frame containing the data has been sent and txe=1, the hardware will be the location ' 1 '. If the Tcie in USART_CR1 is ' 1 ', an interrupt is generated. The bit is cleared by the software sequence (read USART_SR first, then write to USART_DR).     TC Bits can also be purged by writing ' 0 ', which is recommended only in multiple-cache traffic. Rxne: Read data register non-null (read database not empty) when the data in the RDR Shift register is transferred to the USART_DR register, the bit is placed by the hardware, indicating that the data has been received. If the Rxneie in the USART_CR1 register is 1, an interrupt is generated. A read operation on USART_DR can clear the bit to zero.   Rxne bits can also be purged by writing to 0来, which is recommended only in multiple cache traffic. The direct Operation register code is as follows: (System.h and Stm32f10x_it.h and other related code reference STM32 Direct Operation Register Development environment configuration) USER/MAIN.C

01	#include <stm32f10x_lib.h>

02	#include "system.h"

03	#include "Usart.h"

04	#include "stdio.h"

05

06	#define PRINTF_ON 0//Set PRINTF () output