Storage System (2)

Source: Internet
Author: User

Initi6410x supports 32-bit physical address field and that address field can be seperated into two parts, one part
Is for memory, the other part is for pheriperal.
Main Memory is accessed via spine bus, and its address range is from 0x0000_0000 to 0x6fff_ffff. This
Main Memory part is seperated into four areas, Boot Image area, internal memory area, static memory area, and
Dynamic memory area.
Address range of Boot Image area is from 0x0000_0000 to 0x07ff_ffff, but there is no real mapped-memory.
Boot Image area has mirrored () image which points a partial (partial) region
Internal memory area or static memory area.
Start address of boot image is fixed to 0x0000_0000.
Internal memory area is used to access internal ROM and internal SRAM for boot loader, which is also called
Steppingstone. Start address for each internal memory is fixed. Address range of internal ROM is from
0x0800_0000 to 0x0bff_ffff, but real storage is only 32kb. This region is read-only, and can be mapped
Boot Image area when internal Rom booting is selected. Address range of internal SRAM is from 0x0c00_0000
0x0fff_ffff, but real storage is only 4 kb.
Address range of static memory area is from 0x1000_0000 to 0x3fff_ffff.
Srom, SRAM, nor flash,
Asyncronous nor interface device, onenand flash, and steppingstone can be accessed by this address area.
Each area stands for a chip select, for example, address range from 0x1000_0000 to 0x17ff_ffff (128 M) stands for xm0csn [0]. start address for each chip select is fixed. NAND Flash and CF/ATA cannot be accessed via static memory area, so
If any of xm0csn [5:2] is mapped to nfcon or cfcon, related address region shoshould not be accessed. one exception is that if xm0csn [2] is used for NAND Flash, steppingstone is mirrored to address
Region from 0x2000_0000 to 27ff_ffff.
Address range of dynamic memory area is from 0x4000_0000 to 0x6fff_ffff. dmc1 has right to use address
Range from 0x5000_0000 to 0x6fff_ffff. Start address for each chip select is retriable.


The difference between the and is that the 32-bit physical address space is supported and the address space is divided into two parts, one is the storage space and the other is the peripheral space ". The primary bucket is accessed through the spine, and its address space is 0 × 0000,000 0 ~ 0x6fff, FFFF, and primary storage space are divided into four areas: Boot Image area, internal storage area (internal memory area), and static storage area (static memory area) and dynamic storage area (dynamic)
Memory area ).

The address space of the boot image area is 0 × 0000,000 0 ~ 0x07ff, FFFF, but there is no actual memory ing. The Boot Image is mapped to some areas in the internal or static storage areas, and the starting address is fixed to 0 ×.

The internal storage zone provides Boot Loader with access to the internal ROM (internal ROM) and internal SRAM (internal SRAM), also known as steppingstone. The starting address of each internal memory is fixed. The internal ROM address space is 0x0800,000 0 ~ 0x0bff, FFFF, but the actual storage space is only 32 KB. This region is read-only and should be used when the internal ROM is enabled.
Maps to the boot image area ). The address space of SRAM is 0x0c00, 0000 ~ 0x0fff, FFFF, but the actual storage space is only 4 kb.

The address space of the static storage area is 0x1000,000 0 ~ 0x3fff, FFFF, which can be used to access srom, SRAM, nor flash, asynchronous nor interface devices, onenand flash, and steppingstone. Each region corresponds to one slice. For example, the address space is 0 × 1000,000 0 ~ 0x17ff and FFFF correspond to xm0csn [0]. The starting address of each slice is determined. NAND Flash and CF/ATA cannot be accessed through the static storage area. Therefore, if any region corresponding to xm0csn [] is mapped to nfcon or cfcon, the address of the corresponding region is empty.
Cannot be accessed. When xm0csn [2] is used in NAND Flash, steppingstone maps to address space 0 × 2000,000 0 ~ 0x27ff, FFFF.

The address space of the dynamic storage area is 0x4000,000 0 ~ 0x6fff, FFFF, dmc1 has the right to use 0x5000,000 0 ~ 0x6fff, FFFF address space. The starting address of each slice can be configured.

The peripheral space is accessed through the peri bus, and its address space is 0 × 7000,000 0 ~ 0x7fff, FFFF. All special function registers can be accessed through this region. If the data comes from nfcon or cfcon, the data is also accessed through the peri bus.

An article in the two hundred-degree library analyzes that the nor flash stored in 2440 has its own address line and data line. It can use a random access method similar to memory and can directly run programs on the nor flash, therefore, nor flash can be directly used for boot. When nor flash is used for startup, The address will be mapped to 0x00. Mini2440 directly stores VIVI on nor flash.
NAND Flash is an I/O device, and data, address, and control lines are shared. The read time sequence must be controlled in the software area. Therefore, it cannot be accessed randomly like nor flash or memory, it cannot be an EIP (running on a chip), so it cannot be directly used as a boot. In the S3C2440, the bootloader is started on the NAND Flash, because there is a built-in sram in the S3C2440 called stepping stone (stepping stone, very good image ...), After the system starts power-on, it will copy the starting 4 kb of content on the NAND flash to the SRAM for execution, so that it can start from the NAND Flash. If the bootloader is smaller than 4 kb (like vboot), boot will be available in the SRAM. If it is larger than 4 kb (u-boot, Vivi), after some basic initialization in the SRAM, copy the remaining parts of the bootloader to the SDRAM (> 0x30000000 ).
When we use S3C2440, we often start it through nor flash to enter the VIVI menu (the S3C2440 nor Flash has already burned vivi), and then use the USB download function of Vivi, download other bootloaders to NAND Flash and start them through NAND Flash to test our bootloader.
Nor flash is suitable for code storage and EIP, and NAND is suitable for storing large amounts of data.
Nandflash startup: the first 4 K of nandflash memory will be automatically loaded to steppingstone (internal SRAM buffer), and the system will automatically execute the loaded startup code, the 4 K startup code needs to copy the content in nandflash to the SDRAM for execution. The startup code is stored in the first 4 K space of nandflash, and the speed of SDRAM is fast, which is used to execute the code of the main program.

An article from register analysis:

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