Store buffer analysis of or1200 Processor

The following is an excerpt from the book "Step by Step surprise core-software core processor internal design analysis ".

 

14.1 role and working process of Sb Module

Icache is directly connected to the WishBone Bus Interface Unit wb_biu, but a store buffer (SB) module is inserted between dcache and the WishBone Bus Interface Unit wb_biu, as shown in Figure 1.6.

SB accelerates storage operations by buffering storage operations. The principle is as follows: when performing a storage operation, you may need to write data to external memory through wb_biu, especially in the write mode, data is written to external memory for each storage operation. This will wait for external memory to complete the storage operation. During this period, the CPU is paused, reducing the CPU efficiency. After Sb is introduced, if it is a storage operation, the SB module saves the operation and immediately returns a storage completion signal (dcsb_ack_o is 1) to dcache so that the CPU can continue to execute the operation, the Sb module then completes the storage operation that is saved by it. There is a FIFO (first-in-first-out queue) inside the Sb as a buffer. If multiple consecutive storage operations are performed, each storage operation is stored in the FIFO, return the storage completion signal to dcache, and then Sb extracts the data to be saved from the FIFO to complete the storage operation. Figure 14.1 shows how Sb works during storage operations.

The above design has two problems:

(1) Sb directly returns the storage completion signal to dcache, But what if an error occurs during sb's storage to external memory through the wb_biu module?

(2) If the storage operation is still cached in the Sb, that is, the SB has not completed the storage operation, but the dcache initiates the loading operation again, how can we avoid possible data inconsistencies?

The Sb module does not handle the first problem. When using the SB module, you must note that the second problem can be solved by making a judgment before the loading operation is executed, only a blank FIFO can be loaded to avoid data inconsistency. In addition, the load operation is not saved to the FIFO by Sb, but directly handed to the wb_biu module. Figure 14.2 is the SB working process during the loading operation.

SB is a storage buffer module. In terms of name, it is only a buffer storage operation. icache does not have storage operations, but only read commands. Therefore, no Sb module needs to be inserted between the icache and wb_biu modules.

14.2 structure of Sb module 14.2.1 external connection relationship of Sb Module

This section describes the external connection relationship of the SB module, as shown in Figure 14.3. It can be seen that Sb AND dcache, Sb and wb_biu are both WISHBONE bus interfaces, and the CPU has a sb_en signal input to sb, the signal is sb enabling signal, when the signal is 1, it indicates Sb enabling. If sb_en is 0, Sb is forbidden. In this case, dcache is directly connected to the wb_biu module.

In addition, the interface names between Sb AND dcache are in the form of dcsb_xxx_x, and the interface names between Sb AND wb_biu are in the form of sbbiu_xxx_x. Therefore, through the interface name, you can know which two modules the interface is located.

 

14.2.2 internal structure of Sb Module

Source code files that constitute Sb include or1200_sb.v and or1200_sb_fifo.v, which correspond to the Sb and fifo modules respectively. The FIFO module implements a first-in-first-out queue, Which is instantiated in the SB module, the example statement is as follows:

Or1200_sb.v ...... Or1__sb_fifo or1__sb_fifo (. clk_ I (CLK), // input clock signal. rst_ I (RST), // input reset signal. dat_ I (fifo_dat_ I), // data to be saved to the FIFO. wr_ I (writable o_wr), // FIFO write operation. rd_ I (writable o_rd), // FIFO read operation. dat_o (fifo_dat_o), // data read from the FIFO. full_o (fifo_full), // full FIFO flag. If it is set to 1, the FIFO is full. Otherwise, the FIFO is not full. empty_o (fifo_empty) // the first-in-first-out empty flag. If it is set to 1, the first-in-first-out is empty. Otherwise, the first-in-first-out has data );......

See Figure 14.4 In the preceding example. The interface of the FIFO module and the corresponding variables connecting interfaces to sb are provided. The input interface is on the left of each module, and the output interface is on the right, each module is an interface name, and the name on the external pin represents the corresponding variable in sb. Later in this chapter, you need to refer to this figure when analyzing sb. The meanings of the variables in the figure are described in the annotations of the preceding Sample statements.

14.2.3 macro definition related to the SB Module

The macro definition of the SB module in or1200 is as follows:

Or1200_defines.v 'define sequence // No Sb is implemented by default. You need to remove the comment before using Sb 'define or1200_sb_entries 4 // The depth of FIFO 'define or1200_sb_log 2 // or1200_sb_entries base on 2

14.3 sample program

This section provides a simple example program to verify the effect of the SB module, because here we mainly verify the impact of the SB module on the storage commands and want to eliminate the impact of the finger fetch operation, therefore, we still use Chapter 1 to analyze the modified system disk as the verification platform. In this case, the code is stored in qmem, And the finger fetch operation can be completed in one clock cycle without affecting command execution.

Note that you need to modify an error in or1200. See figure 14.3. The Sb enabling signal sb_en is from the CPU module. Refer to the CPU module to see that sb_en is equal to the following:

Or1200_cpu.v 'ifdef or1200_sb_implemented // visible even if Sb is implemented, the sb_en code is commented out // assign sb_en = Sr ['or1200 _ sr_sbe]; 'elseassign sb_en = 1' B0; 'endif

 

This is an error in or1200. The author may have hoped to use or1__sr_sbe, a flag of the special register Sr, to control the startup and stop of sb, however, there is no or1__sr_sbe flag in the SR definition of the special register of or1200. The above code is changed to the following:

or1200_cpu.v`ifdef OR1200_SB_IMPLEMENTED                                           assign sb_en = 1'b1;`elseassign sb_en = 1'b0;`endif

 

So long as the macro or1200_sb_implemented is defined, sb_en is 1, that is, Sb enabling.

The example program is as follows:

. Section. text, "ax ". global _ start. org 0x0 # After resetting the Modified simple FPGA, the command is read from 0x0 of qmem, so the code starts from 0x0 _ start: l. movhi r0, 0x0 # initialize r0, R1, R2, and R3 and set them to 0x0, 0x1, 0x2, 0x3 L, respectively. addi R1, R0, 0x1 L. addi R2, R0, 0x2 L. addi R3, R0, 0x3 L. SW 0x0 (R0), R0 # Save 0x0, 0x1, 0x2, and 0x3 to the RAM address 0x0. SW 0x0 (R0), R1 L. SW 0x0 (R0), R2 L. SW 0x0 (R0), r3

 

The above code is very simple, that is, to store 0x0, 0x1, 0x2, 0x3 in sequence to the 0x0 of RAM.

Create a new file example.s in ubuntu. bin, and mongoram.ldw.makefile=bin2mem.exe to the directory where example. S is located. makefile selects the modified makefile in Chapter 10, that is, it does not use or1ksim for Simulation. Open the terminal, adjust the path to the directory where the above files are located, and enter "make all" to obtain the memory initialization file mem. data that can be used in Modelsim simulation. After modification, you can use this file to initialize the qmem with the simple FPGA. In order to know the commands corresponding to the if_insn, id_insn, ex_insn, and other signals in the simulation waveform, the following lists the binary codes corresponding to the commands, which are divided into three columns, they are the binary corresponding to the instruction address, instruction, and instruction.

Command address: the binary value of the command 0x800000 L. movhi r0, 0x0 0x18000000 0x800004 L. addi R1, R0, 0x1 0x9c200000x800008 L. addi R2, R0, 0x2 0x9c400002 0x80000c L. addi R3, R0, 0x3 0x9c600003 0x800010 L. SW 0x0 (R0), R0 0xd4000000 0x800014 L. SW 0x0 (R0), R1 0xd4000800 0x800018 L. SW 0x0 (R0), R2 0xd4001000 0x80001c L. SW 0x0 (R0), R3 0xd4001800

 

Comment out the macro definition of or1200_sb_implememted, that is, do not use the SB module, as shown in Modelsim simulation waveform 14.5. Do not comment out the macro definition of or1200_sb_implememted, that is, using the SB module, as shown in Modelsim Waveform simulation 14.6. From the comparison of the two waveforms, we can see that the SB module reduces the clock cycle required for storage operations and achieves the design goal.

 

The chapter14 directory on the CD-ROM contains the Modelsim simulation project, and the sample program source code under the chapter14/code directory. Because the SB module is relatively simple, this chapter analyzes the source code of the SB module, analyzes the source code according to the bottom-up sequence, first analyzes the FIFO module, and then analyzes the SB module.