Structure analysis and programming of S3C2440 NAND Flash

After reading the nandflash manual for a long time and some other materials, the manual is a bit dizzy because of poor English. Fortunately, the network resources are rich. To sum up the nandflash operations I understand, I will not continue to program bare metal for some other reasons, just write down all the understandings in detail.

1. There are three aspects to nandflash programming first

1. nandflash memory, of course, this is the focus, because nandflash programming is to perform read/write erasure and other operations on nandflash.

2. nandflash controller. Here, the S3C2440 has been integrated. What we can see is a bunch of registers. For 2440 programming, it is often used to set up a bunch of registers plus timing operations on the device.

3. nandflash pin configuration, because 2440 of Io is generally a multi-function reuse IO port.

2. The second aspect is the structure and operation of nandflash.

1. corresponding to a specific nandflash chip manual, the chip structure is provided. nandflash is divided into two parts: Main erea and spare erea. The main area stores data, the spare area stores additional information, bad block ECC verification, and so on. The structure of NAND Flash is a NAND flash device, 1 (device) = xxxx (blocks), 1 (Block) = xxxx (pages), 1 (page) = 528 (bytes) = data block size (512 bytes) + OOB block size (16 bytes, data block is the main area, OOB is the spare area, except the sixth byte of OOB, generally, the first three bytes of OOB are stored in the NAND Flash hardware ECC code ). The OOB area is available on every page. The page size is 512 bytes. Each page is allocated with a 16-byte OOB. If the NAND is a 2 k page physically, each page is allocated with a 64-byte OOB. For details about the allocation, see the data manual.

2. bad block, if nandflash has no bad block, it will be perfect. However, the nandflash process determines that the bad block of NAND is inevitable (the specific reason should be related to its storage method ), it is precisely because of the existence of Bad blocks that the use of NAND storage becomes complicated. First, the definition of Bad blocks refers to the existence of one or more unknown states in a block.

3. Classification of Bad blocks. Bad blocks are divided into two types. One is the bad block that already exists at the factory, which is inherent in the bad block. For the inherent bad parts, the chip factory has already marked the bad parts. For different chip labels, sangsun is used as an example. The small one is 1 page 512 byte, bad Block checks the sixth byte of spare data.
The big one is 1 page 2048 bytes, and the bad block checks the 1st bytes of spare data. Generally, the sixth byte or the first byte marked on the first and second pages of each block is not 0xff and is generally written to 0. The second is the use of Bad blocks. This part of Bad blocks requires you to create a bad block table for tag management.

4. for bad block management, first of all, attention should be paid to the management of Bad blocks. nandflash reads and writes pages, erases blocks, and erases bad block tags, therefore, you must determine whether the block is bad before performing the operation. I have a good idea on the bad block management network. I think it is very good. For the entire nandflash, there are three areas. The first zone uses information (including bad block tables, use the number of blocks, and reserve 10 blocks). The second zone is the data record area, and the third zone is the bad block ing area (used to replace bad blocks and reserve blocks, data cannot be written directly into it, which is 128 blocks ).

Select a good block from the first 10 blocks to record the bad block information and other information of the entire NAND. Then, the second area is the real data record area, the third area is the replacement area of the Bad block. Run a bad block scan program to create the entire bad block table. The Bad blocks generated later are also recorded in the bad block table. When writing data, first check whether the bad block table is a bad block. If it is a bad block, the data is written to the block in the replacement area.

5. ECC uses Samsung's k9f2g08u0a nandflash as an example to describe my understanding. First of all, ECC is a verification method for error detection and correction. The principle is complicated. Samsung has a document to describe it, it can be implemented using software and hardware. The S3C2440 hardware generates ECC, which simplifies programming. ECC is divided into two parts: ECC in the main area of the master data, and ECC in the spare area. The ECC verification process is as follows. After reading and writing a page of data, the hardware automatically generates ECC data to nfmeccd0/1 (main zone data ECC ), after reading and writing the spare area, the ECC is automatically generated to nfseccd0/1 (spare data ECC ). Then we need to save the two ECC data to the spare area of the NAND. For the k9f2g08u0aspare area, there are 64 bytes. Do not use 1st or 2 bytes, because the bad block mark at the factory is stored in the first two bytes of the first two pages of each block, in order to unify, you will also use one or two bytes to mark the bad block in the future. Use other bytes to save ECC in the main zone and ECC in the spare zone. When reading the data in the main area, the same hardware automatically generates ecc to the nfmeccd0/1 register, and then compares the ECC data that was last saved for the same two times, there is no error, however, we only need to put the retrieved ECC data into the nfmeccd register, and the hardware will automatically compare it. I only need to read the ECC Status Register nfestat0/1 to get the result. Check the spare and handle the errors.

Supplement: I wrote a blog post yesterday and read some books today to add some.

First, my chip is k9f2g08u0b of sangsun, the size of the chip is 256 m. The 8-bit I/O Manual does not specify how many plane the entire chip is divided into. However, I have read the following description and I think the entire chip is divided into two plane.

It is also important to correct that the nandflash storage zone includes the Mian and spare areas, and the nandflash also has the Register-Status Register. After the read/write operation is completed, run the read Status Register command to read the status in nandflash to determine whether the read/write operation is successful. Note that this register is not in nandflash controller in nandflash. The significance of the register value is described later in the manual.