Study summary of the fifth week of Information Security Programming Foundation

Fourth Chapter processor Architecture

4.1 Y86 Instruction Set architecture

First, the programmer visible State

Programmer visible State: Each instruction in the program reads or modifies portions of the processor state

--8 a program register:%EAX,%ECX,%EDX,%EBX,%ESI,%EDI,%ESP,%EBP. They can all store a word ;

%ESP is stacked, stack, call and return instruction as the stack pointer ;

In other cases, the register does not have a fixed meaning or fixed value

--3 a condition code:ZF,of,SF. To save information about the impact of recent arithmetic or logic directives

--PC (program counter): Stores the address of the currently executing instruction.

--Memory: A large array of bytes, preserving the program and data;

Y86 uses virtual addresses to refer to memory locations, and hardware and operating system software unite to translate virtual addresses into actual or physical addresses, indicating where the data is actually stored in memory

--stat: The status code, the last part of the program state, indicates the overall state of the program execution, indicating whether it is functioning correctly or that an exception has occurred

Second, Y86 directive

--halt: This command will terminate the execution of the instruction.

--nop: This is a placeholder instruction, it does not do anything, follow-up in order to achieve the pipeline, it has a certain role.

--XXMOVL: This is a series of data transfer instructions where r represents a register, m represents memory, and I represents an immediate number. For example, the RRMOVL directive assigns the value of a register to another register.

--OPL: Operation instructions, such as addition, subtraction and so on.

--JXX: Conditional jump instruction, according to the following conditions to jump.

--CMOVXX: Conditional delivery instruction, followed by XX is the condition. In particular, conditional delivery occurs only between two registers and does not transfer data to memory.

--call and Ret: Method invocation and return instruction. One will return the address into the stack and jump to the destination address. One will return the address into the PC and jump to the return address.

--push and pop: in-stack and out-stack operations.

C. Instruction code

-For the OPL, JXX, cmovxx directives, there is an FN identifier, which takes up 4 bits (half a byte). This is the functional part of the instruction, which is caused by the same code of instruction, but with different functions. For example, for OPL, there are add, subtract, and, XOR, or other operations, then their instruction encoding the first byte is 16 binary 60, 61, 62, 63.

--byte-level encoding of the visible instruction in the Y86 instruction set diagram. Each instruction requires a range of 1-6 bytes. The first byte of each instruction indicates the type of the instruction. This byte is divided into two parts, each part 4 bits: The height 4 bits is the code part, the low 4 bit is the function part. function values are only useful if a single set of related directives is shared with one code.

--some instructions have only one byte long, because a register designator byte may be attached, specifying one or two registers. These register fields are RA,RB. There are, none, no, only one will set the second to 0xF.

Iv. Y86 Anomalies

-For Y86, there is a stat status code in the visible state of the program Ape, which identifies the state of the program execution. Y86 needs to be able to do some processing according to Stat. But for the sake of simplicity, the execution of the instruction will be stopped in addition to normal execution. In reality, there will be special exception handlers.

--y86 has four different status codes, AOK (normal), HLT (Execute Halt command), ADR (illegal address), and ins (illegal instructions).

V. Details of the Y86 procedure and the Y86 Directive

-for example, Addl $4,%ecx in the X86 directive, because the ADDL directive in Y86 does not contain an immediate number, Y86 needs to deposit an immediate number into the register, which is to use the IRMOVL instruction and then use ADDL to handle the addition operation.

-- the only tool to create Y86 code is the assembler.

-- with "." The first word is the assembly command, which tells the assembler to adjust the address so that it can generate code or insert some data there. Command . Pos0 tells the compiler to generate code starting at address 0. This address is the starting point for all Y86 programs.

4.2 Logic Design and hardware control language HCL

First, the logic gate

--The output generated by the logic gates is a Boolean function that equals their input bit value.

--AND &&

OR ||

NOT !

Ii. combinational Circuits and Boolean expressions

--The output generated by the logic gates is a Boolean function that equals their input bit value.

--the output of two or more logic gates cannot be connected together, otherwise the signal on the line may be contradictory, resulting in an illegal voltage or circuit failure.

--The net must be without rings.

Three, word-level combination circuit and HCL integer expression

-- all word-level signals are declared as int, and the size of the word is not specified

-- The arithmetic /logic unit (ALU) is a very important combination circuit, with three inputs, labeled A,b two data input and a control input. Depending on the settings of the control input, the circuit performs different arithmetic or logical operations on the data input.

Iv. Set Relationship

-- The general format for judging set relationships is:iexpr in {iexpr1,iexpr2,...,iexprk}

V. Memory and Clock

--Clock Register (register) store single bit or word, clock signal control register load input value

--Random access memory (memory) stores multiple words, using the address to select the read or which word to write

sequential implementation of 4.3 Y86

First, the process is organized into stages

--refers to: the reference stage reads the instruction byte from the memory, the address is the value of the program counter PC

--Decoding: decoding phase reads up to two operands from the register file

--Execution: In the execution phase, the arithmetic /logic unit either executes the instruction specified by the value of the Ifun, the valid address referenced by the computer memory, or increases or decreases the stack pointer

--Access: The data can be written to memory or read from memory during the visit

--Write back: Write back stage can write up to two results to register file

--Update PC: set the PC as the address of the next instruction

Second, SEQ hardware structure and timing: Reading on the P258 map

Three, the realization of the SEQ stage

--Take the finger stage : The reference stage includes the instruction memory hardware unit. As the address of the first byte (byte 0) of the PC, the unit reads 6 bytes from memory at a time , the first byte is interpreted as the instruction byte, and is divided into two 4-digit numbers. Thecontrol logic blocks labeled "Icode" and "ifun" Calculate instructions and function codes equal to read values from memory, or when the instruction address is not valid (Imem_error indicated), these values correspond to the NOP instruction.

--Decoding and writeback phase: All access to the register file. The register file has four ports, supports simultaneous two reads (Ports A,B), and two writes (E,M), each with an address connection and a data connection. Depending on the instruction code Icode and the register indicating values RA and RB, the CND condition signal may also be calculated based on the execution phase .

--Execution phase: The execution phase includes the ALU calculation for each instruction in the first step of the Arithmetic/logic unit (ALU), and the execution phase includes the condition code register.

--the stage of the visit: The mission is to read or write the program data, the two control blocks generate the memory address and memory input data value, and the other two blocks to produce a control signal indicating whether to perform read or write operations. The data memory generates a value Valm when the read operation is performed .

--Update PC stage: Thelast stage in SEQ produces a new value for the program counter, depending on the type of instruction and whether to select the branch, the new pc may be Valc,valm,valp

* Laboratory Building

* Problems encountered

I hope the teacher will explain why the instruction Pop%esp, will make the function return OXABCD, and other Y86 instructions

* Reference

-The most important of course is the book, many of the concepts are according to the book

-Reference to Shang's blog, mainly to see her focus on learning where, I also learn

Study summary of the fifth week of Information Security Programming Foundation