Suitable for storage and display test module with FIFO Interface Challenge CB

CB said perfect is no limit, to this I agree, since the use of CB Board, play open CMOS,FPGA,SDRAM,VGA and so on.

Constantly emerging is, dual-port SDRAM, four-port SDRAM, a variety of packages, but the same, but always a little different, for beginners I, feel still quite trouble, play a variety of routines found, CB SDRAM driver is very powerful but not perfect, wherein the SDRAM has a selection role, If hy57v641620ftp-7 is OK to use, change to hy57v641620ftp-6 there is a problem, but the use of other versions of the program testing, these two ICS are OK.

This problem once troubled CB long, eventually CB accidentally found, will burst length from 256 to 128, can be a good solution, since then, solve the problem (see CB Blog for details)

But this may not be perfect, need to delve into its root, you have to carefully read the internal code, careful scrutiny, I have limited level, so can only step by step.

Compatible and incompatible programs are now unified interface, making the program better transplant, logic clearer.

PS:CB interface has done great, but I'm not used to, the following porting interface, according to my thinking to understand the way to modify.

First look at the existing CB interface

In the transformation

1.

Module Lcddata_simulate
(
Inputclk,//globan Clock
Inputrst_n,//global Reset
Inputsys_vaild,//the device is ready
input[7:0]divide_param,//0-255
INPUT[11:0] x_size,// increase X size input,
INPUT[11:0] y_size,// increase Y size input,

SYS 2 SDRAM control
Outputdisp_valid,// increase the display of valid signal output, inform the device, the current output pixel is valid, similar to the display of the frame synchronization signal
Outputreg[15:0]sys_data,
Outputsys_we
);

2, Sdram_vga_display_test

Increase the wr_load signal, according to the data generated the frame of the module valid signal, generate a pulse, high-level pulses, at the end of the frame synchronization signal generated, to clear the FIFO

Wire wr_load;
Reg SYS_DISP_VALID_R1;
Reg SYS_DISP_VALID_R2;
[Email protected] (Posedge clk_ref)
Begin
sys_disp_valid_r1<=sys_disp_valid;
sys_disp_valid_r2<=sys_disp_valid_r1;
End
Assign wr_load=sys_disp_valid_r1& (!SYS_DISP_VALID_R1);

3, Sdram_vga_display_test

FIFO Write Side
. WR_CLK (Clk_write),//write FIFO clock
. Wr_load (Wr_load),// Use this signal
. Wr_data (sys_data_in),//write DATA input
. WR (sys_we_in),//write data request
. WR_MIN_ADDR (D0),//write start address
. WR_MAX_ADDR (' H_disp * ' v_disp *22 ' D1),//write MAX address
. Wr_length (9 ' d256),//write burst LENGTH

In this regard, the first step of compatibility has been completed, this goal has reached the data generation module at any interval to produce data, to ensure synchronization, and repeatedly realize the display size automatic matching function.

Suitable for storage and display test module with FIFO Interface Challenge CB