Summary of FPGA pin allocation considerations

1. Flow of signals carried by FPGA at the board level.

Generally, the strip of a Board follows the signal stream. from one side to the other side, it may be bent, but it will not return. FPGA pins are allocated.

This principle should also be followed to avoid wiring, such as crossover and surround.

 

2. FPGA internal bank.

Be familiar with the internal distribution of the FPGA chips used: How many banks are there, how each bank is distributed, and what level standards are supported, note that one bank of FPGA can only work under one level standard, that is, all Io ports of the same bank can only be of the same level standard.

 

3. Special signal pin distribution, usually refers to the clock and reset signal, also includes some drive capabilities or fan out relatively large signals.

Generally, such signals must be distributed to global clock signal pins. It should be noted that the chips of different manufacturers may have different clock domains. As a result, some clock pins are global clock domains, some are regional or secondary clock domains. In addition, the clock pins are usually paired because some clocks are different. If only one pin is used, the other cannot be used as different clocks (in Xilinx ).

 

4. A large number of flipped signals are separated, which is conducive to signal integrity.