Summary of invalid assembly language commands

Problem: The cmpxchg8b command compares an eight-byte value of edx and EAX with eight-byte memory (destination operand ). Only valid target operands are used for this command as memory operands. If the target operand is a register processor, an invalid OpCode exception should be generated, the executed command cmpxchg8b should be stopped, and the processor should execute an invalid OpCode exception handler. This error occurs when the lock prefix uses the cmpxchg8b command with an (invalid) Register destination operand. In this case, the processor may not be able to start an invalid OpCode exception handler because the bus is locked. This will cause system suspension.

Tip: If (invalid) Register destination operations use the cmpxchg8b command and lock prefix, the system may suspend. If no memory data is damaged, you can perform a system reset to return to the normal operation. Please note that this error is required for specific invalid code sequences and cannot be generated normally. The programming of this course is not such a sequence of cocoa from this commercial software.

This error applies only to Pentium processor, Pentium processor and MMX technology, Pentium OverDrive processor, and Pentium OverDrive processor with MMX technology. The Pentium Pro processor, Pentium II processor, and IMG and earlier processors are not affected.

Work und: There are two work und: this error protects the operating system in the mode. Work und: both generate a page error when OpCode is invalid. In the above two cases, page errors will invalidate the OpCode exception before repair, so as to prevent the occurrence of lock status. Implementation Details will vary depending on the operating system. Use one of the following methods:
The first seven entries (0-6) of the solution set in the first part interrupt description table (IDT) are on the non-write page. When the OpCode is invalid (exception 6), the cause is that the cmpxchg8b command is locked with an invalid registered destination ), the processor generates a page error if no write access to this page contains the IDT of entry 6. The second part of this solution changes the page error handler to understand and correctly Schedule "invalid OpCode exceptions, now wiring through the page error handler.

Access Part I and IDT pages

The IDT that marks the first seven entries (0-6) contained in the page is read-only. You can also set cr0.wp (16 bits) to 1. Now, when the "invalid OpCode exception occurs to lock the cmpxchg8b command, the processor will trigger a page error because it does not write the IDT that accesses the page containing entry 6. This page error blocks the bus lock status and gives the operating system full control of the process "invalid operation exception. Note that exception 6 is an invalid OpCode exception. Therefore, any program with full control of the operating system in this schema executes an invalid cmpxchg8b command.
Optional. These page errors prevent alignment IDT from crossing a 4 kb page boundary (for example, the first seven entries (0-6) the IDT of is on the first read-only page and the remaining entries are on the read/write page.

II. Page error handling program modification

Modify the paging volume processing program to calculate which exception causes the page to use the capacity address cr2. If an exception occurs on the error code stack, the system starts from alarm 0 and the address corresponds to an invalid OpCode exception. Then the pop-up error code closes the stack and jumps to the "invalid OpCode exception handler. Otherwise, the normal page error handling program will continue.
Or
The solution consists of two parts. First, the interrupt description table (IDT) is aligned (for example, any invalid OpCode exception may cause a page error (because the page does not exist ). Second, page error handler date recognition and correct scheduling "invalid OpCode exceptions and other exceptions, now wiring through the page error handler.

Calibration of Component I and IDT:

Alignment interrupt description table (IDT), which spans the 4 kb page boundary and starts the first entry 56 bytes from the final 4KB page. This puts the first seven entries (0-6) on the first 4KB page and the remaining entries on the second page.
The IDT of the first 7 entries contained in this page cannot be mapped to the OS page table. This will cause no fault in generating a page with any exception 0-6. A page error blocks the bus lock status and gives the operating system full control over these exceptions. Note that exception 6 is an invalid OpCode exception. Therefore, any program with full control of the operating system in this schema executes an invalid cmpxchg8b command.

II. Page error handling program modification:

Identify the access to the first page of IDT passed the test in the capacity address cr2. The page does not have a fault and can be processed properly at other addresses.
The page does not contain the IDT on the first page of the fault. The operating system must identify and send the exception to cause the page to not have a fault. Before proceeding, test the fault address with cr2 to determine whether it is in the range of the corresponding exception 0-6.
Which of the following causes the page to fail.
Depending on the operating system, certain permission level checks may require, and adjustments to the interrupt stack.
Jump to the normal processing program for appropriate exceptions.

The Two workarounds should only implement intel processor return family = 5 via CPUID command.