Summary of PowerPC startup Methods

1. Basics

1.1 CPU address space

Local address map is the 36bit address space that core can access. This address space includes the address space that each function module can access, the ddr sdram space, and the CCSR address space. How does the CPU core access various functional modules on the SOC? For example, elbc controller, DDR controller, and PCI Controller. It is configured through the Law (local access window) Register. Each law register connects an address space to the corresponding functional module, and compares the physical address from the core with the address of each law. If the address space specified by a law is, then, send this message to the function module specified by this Law. Each law can specify a 4 K-32G address space.

[Note]: The lawba [base_addr] domain must be aligned with the address space.

 

There are three special addresses in this address space:

A. CCSR address space: you only need to specify the starting address through the ccsbar register. The address space is 1 MB (e500core is 1 MB and e500mc is 16 Mb ).

The default value of ccsrbar (configuration, control, and status registers base address register) is 0xff700000.

When setting the TLB to access the space, you need to set the I and G locations 1.

B. l2sram address space

The mpc8536e has a K l2cache, which can be configured to be used by SRAM. In this case, the l2sram size needs to be specified through the l2ctl [l2sram] domain, and the actual address is specified through the l2srbar register.

C. Default 8mbootrom address space

Generally, the SOC defines 8 Mb bootrom startup address space (0xff80_0000-0xffff_ffff). When the core is reset, the first command can directly access the address space of the specified Startup Device. Enable the device to specify nandflash and nor flash mounted on elbc, or the SD card/spiflash.

Priority of the preceding Address Space Configuration:

The address specified by l2srbar takes precedence over the address space specified by other methods;

The address space specified by ccsrbar cannot be the same as the address space specified by the DDR controller. Otherwise, the CPU behavior is undefined;

If the addresses of law are repeated, the low-encoding law overwrites the address space of the High-encoding law.

1.2 TLB

TLB is simply a query table that converts a virtual IP address of a program into a physical IP address. TLB uses the wimge field to specify the properties of the accessed address space.

At startup, tlbentry in all L1/l2mmu is invalid. Except for the tlb1 entry0, this entry is assigned the following value to specify the address space 0 (as0) the 4kb start address space (0xffffff_f000-0xffff_ffff ). In the U-boot code, this 4 K code is called bootpage, that is, the bootpg assembly code in CPU/mpc85xx/start. S.

When the e500 core is reset, it will go to 0xffff_fffc to read the first command. This command is generally a jump command and jumps to the bootpg header for execution.

2. bootfrom nor flash

Generally, nor flash is attached to the elbc controller of the CPU and selected through CS0. To start from nor flash, first burn the compiled 512 k u-boot image to the last K of norflash. When CPU core is started, the first command is executed at 0xfffffffc. Generally, a jump command jumps to the bootpage, because nor flash is accessible in bytes, the CPU then executes the code in nor flash sequentially.

2.1 elbc

Elbc uses gpcm to connect to norflash and FCM to connect to NAND Flash.

Br0/OR0-BR7/or7 specifies the address space and properties for the elbc8 chip selection signal. CS0 connects to the Startup Device. For example, when starting from norflash, nor flash must be connected to CS0. When starting from nandflash, NAND flash must be connected to CS0. For a single board with both nor flash and NAND Flash, and supports two startup modes, the CPLD is required to dynamically switch the CS0 chip selection signal to the Startup Device.

When you choose to start from nor flash, CS0 is used as the boot chip selection signal output. The selected address and space are determined by br0 and or0 information. The starting value of this register is as follows, apparently, the 4G address space from 0-0xffffffff is accessed. The signal selected for this film continues to run in this way until the br0 or or0 value is changed for the first time.

When the U-boot program is burned to nor flash, the 512k image is written to the last 512k byte of flash, that is, the start point of eff8_0000. When the core is started, the first command is ffff_fffc. Actually, the command at efff_fffc is read (0x4bff_f004 ).

2.2 Startup Process

The first question is, which address does U-boot image need to be burned to nor flash? It is determined by the hardware connection between the CPU and norflash. This address also determines the config_sys_text_base value of U-boot. The value is assigned to-ttext In the config. mk file, that is, the starting address of the text segment in the U-boot image.

3. bootfrom NAND Flash

3.1 text_base

Why is the text_base device 0xf8f8_2000 when starting from NAND.

Because we need to combine the 4 k nand loader and the second-stage image (using the cat command), and then burn it to the NAND Flash. At startup, FCM will copy 4 knand loader to fcm ram buffer, while 4 knand loader and the second-stage image will be copied to l2sram. I configured the l2sram address as 0xf8f80000, 4 knand loader, and 4 K bootpg, so the text segment of the second stage should be at 0xf8f82000.