SV Build Verification Environment

1) The first definition of pure virtual class Sv_object, the main implementation of the following two function:

Define local static variable Nextobjectid;

virtual function void Copy (St_object, Clonetype clone_type = deep), and copy in base class can be iterated by super.copy.

2) The encapsulation of mailbox and event is realized on the basis of sv_object. Produces two base classes Sv_mailbox_wrapper and Sv_event_wrapper. Where event is more used in Process control

(Wait (event), event (trigger) and so on function), mailbox is mainly used in the transaction of the delivery.

3) on the basis of Sv_object, a sv_testobject pure virtual class is established, which is used as the base class for validating the various components in the environment, and implementing 4 Funciton,start,stop,main,reset in the base class. Use

The event links these several funciton. This gives you a basic flow of control.

4) The establishment of the transaction class, this class does not count the components in the validation environment, so use Sv_object to extends. However, it is also essential to establish basic processes in the Sv_transaction class, such as:

Generate,execute,check. respectively in generator segment, driver, Monitor,dut segment, check segment. Also implemented by event, you can implement three function to control this

Three event, called in the upper layer to implement callback. It's all a process for a tranaction.

5) The establishment of the generator base class, on the basis of Sv_testobject extends, to redefine a generate function, to allow testcase to redefine, complete generator

And some exceptions to the constrain, or other callback functions.

6) The establishment of driver base class, on the basis of Sv_testobject extends, because of the need to add the additional reset signal, so on the basis of Sv_testobject, add another two higher priority

function, where the priority is implemented through event blocking, Wait_for_reset, reset.

7) Monitor base class establishment, on the basis of Sv_testobject extends, mainly on the basis of sv_testobject defined a Receive_trans function, to receive signals from the DUT.

8) Check base class establishment, on the basis of Sv_testobject extends, this class is related to the specific test is larger, the base class only need to define some event to represent start and done.

9) Test base class establishment, on the basis of Sv_testobject extends, this class is mainly to complete the control of the process, can be divided into genconfig (), Configdut, build (), start (), Stop, Report,

The overall configuration of the environment, in the configuration of the DUT, then clock, reset, signal came in to complete the initialization, and then start to verify the platform of the various modules to work, at this stage again according to the transaction three

function to subdivide the control.

The establishment of the Test_trans class, based on the transaction extends, is mainly for the randmize definition and constrain of the signals in the DUT, and the need to establish a Param_trans

function, which is mainly to pass transaction, so that the corresponding mailbox can be linked after the function is directly instantiated at the topmost level.

One) the establishment of the Test_generator class, based on the generator base class extends, is mainly to redefine generator this function, that is, to complete randomized and some exceptions constrain, or

The other callback functions. Also establish a Param_trans function to receive transaction from Test_trans. The top layer is instantiated and mailbox connected.

The establishment of the Test_driver class, based on the driver base class extends, is mainly added to reset's control, redefining the driver base class Wait_for_reset and reset two function. also establish a

The function of the Param_trans receives the interface virtual interface from the Test_generator transaction and CLK, Reset, Dut. The top layer is instantiated and mailbox connected.

The establishment of the Test_monitor base class is extends based on the monitor base class, which collects part of the DUT signal. Also create a Param_trans function that can be composed of the collected signals

A transaction sent to Test_check can also introduce some CLK, reset's interface virtual interface. The top layer is instantiated and mailbox connected.

The establishment of the Test_check class, based on the check base class, defines some very detailed function to match the expected behavior according to the transaction received. also establish Param_trans

function to accept the transaction from Monitor. The top layer is instantiated and mailbox connected.

The establishment of the TestCase class, based on the test base class, is extends, mainly configuring the validation environment, redefining Genconfig (), Configdut the two function, and in the build function, instantiate

Each component of the Param_trans function, to connect the various mailbox together.

16) Define a testbench_top module, the main example of Dut_module, dut_if, clk_if, reset_if and other RTL files.

16) Define a program, instantiate Testcase.sv, top. The entire environment starts executing in initial by invoking the Genconfig () in a testcase.

Finally need to join COVER_FILE.SV and ASSERT_FILE.SV, these two files do not need very complex inheritance, directly according to TestCase definition is good, generally also need the corresponding interface signal, to connect with the DUT

Pick up. Cover_file_if, assert_file_if. It's good to bind the top layer directly through bind top. The need to modify coverage and SVA can be modified directly, they do not affect the entire verification environment.

Additional modules that define reset and clock are placed in the module. Their cover_file and Assert_file are also best tested separately.

The register in the DUT can be obtained through the monitor, where test_regif is positioned through bind XXXX to the level module where the register is located in the DUT.

Of course, this is just some of the most basic modules, as well as the log file in this environment how to design, scripting problems and so on.

SV Build Verification Environment