[Switch] eliminating glitch issues in FPGA design

I. field programmable gate array (FPGA) features high capacity, strong functionality, and high reliability.CommunicationIt is widely used in the system. Using FPGA to design digital circuits has become one of the main design methods in the field of digital circuit systems. In FPGA design, glitch is a long-term problemElectronicsOne of the design problems of design engineers is the main factor affecting the efficiency of design and the effectiveness and reliability of digital system design. Because of the delay caused by signal cabling inside the FPGA and passing through the logical unit, the output of the combined logic often produces some small spikes, that is, Glitch signals, this is determined by the internal structure of FPGA. Glitch is inevitable in FPGA design. Sometimes any glitch can lead to system errors, especially for circuits sensitive to the peak pulse or pulse edge. Therefore, it is particularly important for modern digital system design to overcome and solve the glitch problem. This article discusses the causes and conditions of glitch generation from the perspective of FPGA's principle structure. On this basis, it summarizes a variety of different elimination methods, at last, we will analyze the solution in depth based on specific applications.

1Causes of glitch
 
The example in Figure 1 analyzes the cause of the glitch: Figure 1 is a three-bit synchronous addition counter. When the enable end is highClockThe QA, QB, and QC of the rising edge gradually change from 000 to 111. after entering the full 1 state, the carry output end outputs the high of half the clock pulse width, however, from the simulation result in Figure 2, we can see that there was a sharp pulse in Roc from 011 to 100, that is, glitch.

Figure 1 three-digit counter

Figure 2 simulation results

Analyze the internal structure of Xilinx FPGA, as shown in figure 3.

Figure 3 Internal Structure of FPGA

The FPGA chip is composed of input/outputblock (IOB), cinfigurable Logic block (CLB), andProgrammingProgrammable interconnect array (PIA. The IOB is located around the chip, with the internal logical array and external chipEncapsulationA Programmable interface is provided between pins, which consists of logic gates, triggers, and control elements. CLB is a core array of FPGA and can complete the logic functions specified by users. Each CLB consists of a combination logic, several triggers, multiple power grids, and control units; pia is located between the logical blocks inside the chip and is programmed to form a wired network. It is used to connect the internal logic of the chip and transmit information between them. As shown in figure 3, the cabling from different inputs 1 and 2 to logical blocks (m) may be different, which causes the input signal delay, suppose 1 and 2 are changing at the same time. Due to the delay, there will be first and then there will be at M (this phenomenon is called competition), and there may be dangers (also called adventure) at the logical output end ), A glitch is generated. In the 011 state in the above example, it is assumed that QA and QB change from 1 to 0 at the same time, while QC changes from 0 to 1 in advance to generate a high level of 2ns, which is a glitch. That is to say, in FPGA design, the root cause of glitch is the delay of signal cabling inside the chip.

2Conditions for producing Burrs
 
Use the same example to analyze the conditions for burr generation. QA, QB, and QC flip at the same time on the rising edge of each clock. However, due to the delay, the wiring length from QA, QB, and QC to d triggers cannot be consistent. If QC is 2ns ahead of QA and QB, the state of 2ns is full 1, which is called "illusion full 1", which leads to a sharp Pulse Produced by the carry output. It is worth noting that when 3 is changed to 4, that is, 100 to, two of the three bits are flipped at the same time, that is, there is a signal greater than one at the same time. Due to the delay, the time when multiple signals arrive at the end is first followed by competition. The error output produced by competition is a glitch. Therefore, a glitch occurs when multiple signal inputs change at the same time.

3Burr Elimination Method 

Once you know the conditions for burr production, you can change the design and destroy the conditions to reduce the occurrence of the burr. For example, the gray-code counter outputs only one hop at a time to replace the normal binary counter to avoid glitches. The circuit can also be improved to eliminate the impact of glitch on the system. The following describes the methods:

3.1Redundancy 
There are two ways to use redundant items to Eliminate Glitch: algebra and Kano graph. Both methods eliminate danger by adding redundant items, but the former is for function expressions and the latter is for truth tables. Taking Kano diagram as an example, if two cart circles are tangent, the corresponding circuit may produce danger. Therefore, modify the Kano diagram and add a circle at the tangent of the two circles of the Kano diagram to add additional items to eliminate logical adventure. However, this method cannot eliminate the glitch generated by the counter type.

3.2Sampling Method 
Because the adventure occurs more often when the signal has a Level Jump, that is, there will be a glitch during the time when the output signal is established, but it will not appear during the holding time. Therefore, sampling the output signal within the maintenance time can eliminate the influence of the glitch signal. There are two common sampling methods: one is to use a certain width of the High Level Pulse and the output phase, this avoids the glitch signal and obtains the level value of the output signal. This method must ensure that the sampling signal is generated at the appropriate time, and is only applicable to situations where the output signal timing and pulse width are not strictly required. Another more common method is the locking method. It is the feature that the input D of the D trigger is not sensitive to the glitch signal. Within the holding time of the output signal, use a trigger to read the output signal of the combination logic. Q = D at the output end of the rising time of the clock. When the input signal has a glitch, as long as it does not occur at the rising time of the clock, the output will not have a glitch. This method is similar to converting an asynchronous circuit into a synchronous circuit, which is easy to implement, but also involves timing issues.

3.3Absorption Method 
Because the glitch is actually a high-frequency narrow pulse, the output filter is added, and the glitch can be filtered out by connecting a small capacitor C at the output end. However, the front and back sides of the output waveform will deteriorate. When the waveform requirements are strict, an shaping circuit should be added. This method should not be used in the intermediate stage.

3.4Latency Method 
Because the glitch is ultimately caused by delay, you can find the branch that produces the delay. For branches with relatively low latency, The glitch can be eliminated by adding the delay of the burr width. But sometimes with the increase of load, the glitch will continue to appear, and when the temperature changes, the added voltage changes or the logic gate needs to be increased, the added delay is different, and the delay line must be re-designed, therefore, this method also has limitations. In addition, the delay line method will cause the system reliability to deteriorate due to changes in the ambient temperature.

3.5Hardware Description Language Method 
This method is to start with the hardware description language, identify the root cause of the glitch, change the language design, and generate functional modules that meet the requirements to replace the original logical functional block. In the circuit shown in figure 1, a three-digit counter may cause a glitch when the switch between 011, 100, and 101 to 110 occurs. The reason is that there is a jump between two digits at a time, availableVHDLThe language writes the counters as follows, and the generated counting module replaces the original ordinary counters.
Subdesignmodcount
(CLK, reset: input; Q [2110]: output ;)
Variable
Counter3
: Machineofbits (R [2110])
Withstates (R0 = B "101 ",
R1 = B "100 ",
R2 = B "000 ",
R3 = B "001 ",
R4 = B "011 ",
R5 = B "010 ",
R6 = B "110 ",
R7 = B "111 ");
Begin
Q [] = RR [];
Counter31reset = reset;
Counter31clk = CLK;
Casecounter3is
Whenr0 => counter3 = R1;
Whenr1 => counter3 = R2;
Whenr2 => counter3 = R3;
Whenr3 => counter3 = R4;
Whenr4 => counter3 = R5;
Whenr5 => counter3 = R6;
Whenr6 => counter3 = R7;
Whenr7 => counter3 = R0;
Endcase;
End;

Note that in the new Counter, each time the status changes

Ii. fault generation in FPGA Circuits

We know that there must be latency when signals are connected through logical units in FPGA Devices. The delay is not only related to the length of the line but also to the number of logical units, but also to the manufacturing process and working environment of the device. Therefore, the time required for signal transmission in the device cannot be accurately estimated. When multiple signals change at the same time, a "Competitive Adventure" occurs ". At this time, there will often be some incorrect peak signals, these peak signals are "glitch ". In addition, because the distributed capacitance and inductance in FPGA and other CPLD devices have no filter effect on the glitch in the circuit, therefore, these glitch signals will be "retained" and passed to the next level to make the glitch more prominent.

It can be seen that, even in the simplest logic operation, if multiple signals jump at the same time, after going through the internal line, there will be a glitch. Currently, signals used in digital circuit design and digital signal processing are usually controlled by the clock. complex computing systems with multiple data inputs, and even each data is composed of a considerable number of digits. At this time, each level of glitch will have a serious impact on the results. If it is a multi-level design, the burr accumulation may even affect the reliability and accuracy of the entire design. The multiplication circuit is used to describe the burr generation and removal. In the experiment, the program software we use is us ii2.0, and the experimental device is cyclone ep1cf400i7. Note that, because the oscilloscope cannot display the result of this integer operation, we will only provide the software simulation results here. We will not detail the specific programming and program download here. You can refer to relevant literature and books.

Burr Elimination Method

First, we will design a simple multiplication circuit. Circuit 1.

 

Figure 1 Multiplication operation circuit and Result

 

1 (c) shows that if no burr removal measures are added, we can see that result C contains a large number of glitches. The reason is that the data on each data line of each input (a and B) cannot arrive at the same time on the rising edge of the clock. That is to say, when the clock reads data on the data line, some data lines read new data, while some data lines read the previous data, which will undoubtedly produce glitch signals. when the data is completely stable, the glitch signal disappears naturally.

Add a D trigger to the output

This is a traditional way to remove glitches. The principle is to use a D trigger to read the glitch-carrying signal, and use the D trigger to remove the glitch in the signal because it is insensitive to the glitch of the input signal. This method is a common method in a simple logical circuit, especially for the glitch signal that occurs in a non-clock hop edges.

However, for most time series circuits, Glitch signals often occur along the hop of the clock signal, so that the effect of the D trigger is less obvious (see Figure 2, Q output after the D trigger is added, which still contains glitch ). In addition, the use of the D trigger will bring a certain delay to the system, especially when there are many system levels, the delay will also increase. Therefore, when the D trigger is used to remove the glitch, it depends on the situation. Not all glitches can be eliminated using the D Trigger.

 

Figure 2 Calculation circuit and result after adding the D Trigger

 

Signal synchronization method

As mentioned in many articles, synchronous circuits can be used to design digital circuits to greatly reduce glitches. In addition, because most of the burrs are relatively short (about several nanoseconds), as long as the burrs do not appear in the clock hop variation, the glitch signal will not cause harm to the system. Therefore, many people think that as long as the same clock is used in the entire system, the system synchronization goal can be achieved. However, there is a very serious problem here, that is, when the clock signal is the same as all other signals, there is a delay when transmitted in FPGA Devices, in this way, it is impossible to predict the exact position of the clock hop edge. That is to say, we cannot guarantee that the data read along the hop of a clock is a stable data, especially in the multi-level design, this problem is even more prominent. Therefore, achieving real "synchronization" is the key to removing glitch signals. I think the key to synchronization here is to ensure that the data read at the clock hop-and-hop edge is stable data rather than glitch data. Taking this idea as the starting point, the following signal synchronization methods are proposed.

Signal Delay Synchronization Method

First, we give the calculation result of a two-level multiplication (C = a B; q = D C) (3, the circuit is no longer provided here ). We can see that when no processing process is added, the two-level result C and Q contain a large number of glitch signals. Among them, the glitch signal is generated because the data signal is changed at the same time when the clock hop is calculated. In addition, the first-level signal C contains a large number of burrs, which are obviously amplified after the second Multiplication operation. As shown in figure 3, Q is more serious. But in a lot of practical work, what we are most concerned about is the final output result (q ), as long as the glitch of the intermediate signal has no effect on the subsequent output, we do not need to process them any more. Therefore, the core idea of signal synchronization proposed here is to eliminate the influence of these intermediate glitch signals.

 

Figure 3 Result Simulation of two-level Multiplication

 

The principle of the signal delay method is to add a delay link during two-level signal transmission to ensure that the data read in the next module is stable, that is, no glitch signal is included. The signal delay mentioned here can be the data signal delay or the clock signal delay. Due to the length, here we mainly describe the principle of the signal delay method based on the delay of the clock signal. The principle and Result 4 of the above calculation process and the time delay of the clock signal are shown.

 

Figure 4 two-level Multiplication operation and result with clock delay added

 

In Figure 4, clkdelay is the phase of clock delay. The previous clock signal in this step was directly connected to Module B, so that the two modules use the same clock and it seems that synchronization has been done, but as shown in figure 3, the results contain a large number of burrs, which are the root cause of the glitch-the phenomenon of "Competitive Adventure" has not been fundamentally eliminated. The function of adding a clock delay link is to fundamentally eliminate the "Competition Risk". The process is to control the clock delay of Module B for a period of time, the control clock of Module B has stabilized the data C in the previous hop, that is, data without glitch signals. At this time, data D has reached a stable level, which eliminates the risk of competition, thus, the glitch signal is effectively restrained, as shown in 4 (c.

Similar to the clock delay method, we can also eliminate the risk of competition in the data signal plus delay to achieve real synchronization. The latency here can be achieved using the lcell provided by Quartus ⅱ, or the D Trigger and a high-frequency counting pulse. In addition, we can also see from the comprehensive results (Figure 4 (c) that the added latency occupies a small amount of chip resources, which is a simple and effective way to save resources.

Flexible Use of clock signals

Similar to the principles of the above method, the purpose of flexible use of clock signals is to eliminate the risk of competition as much as possible. For example, when the first hop-to-hop trigger module A and the next hop-to-hop trigger module B of the clock, the switching control of the clock also eliminates the risk of competition to a certain extent, thus, the glitch signal is blocked. For example, use the rising or falling sides of the clock to control different modules. However, these methods are not suitable for complicated design. Otherwise, they will lead to a very chaotic design and cause great difficulties for future reading and modification. Therefore, be careful when selecting this method.

State Machine Control

For large-scale digital circuit design, the state machine is an ideal choice, which can optimize the running performance and consumption of hardware resources, in addition, the flexible use of the state machine can also achieve signal synchronization and Eliminate Glitch. In a complex multi-module system with data transmission, the state machine sends clock signals or module enabling signals that control specific modules at specific times, the cyclic control of the state machine allows the whole system to coordinate operations and reduce glitch signals. As long as we process the triggering time of the state machine, we can avoid the risk of competition and thus suppress the emergence of burrs. Principle 5 is shown.

 

Figure 5 State Machine Control Principle

 

Due to space limitations, we will only discuss the principle of state machine control and propose a new idea.

Summary

Since the glitch signal has a great impact on the operation of FPGA Devices, how to effectively suppress the glitch signal becomes a very prominent issue. However, it must be emphasized that we must first optimize and improve the program design to minimize the generation of glitch signals, such as replacing some signals with variables to reduce latency. In addition, it is also very important to choose a suitable method in practical applications, so we must carefully consider it. For example, the addition of the delay link will increase the latency of the entire system. If too many links are added, the operation of the system will be affected.

[Switch] eliminating glitch issues in FPGA design