Sylixos PPC Architecture Series Introduction-cache

1. CacheIntroduction

Cache: Cache is a small, but high-speed memory that is located between the CPU and the main memory DRAM (dynamicrandomaccessmemory), usually by SRAM ( Staticrandomaccessmemory static memory ) . It is a small but high-speed memory located between the CPU and memory.

2. SylixosinCacheArchitecture

in order to effectively manage The Cache, Sylixos provides the API layer's system interface and hides the differences between hardware architectures. Under different CPU architectures, the Cache operation interface of the Arch layer is also encapsulated separately .

2.1      ApiLayerCacheInterface

The API interface code in the Cache layer package in Sylixos is located in the/libsylixos/sylixos/kernel/cache directory, including cache.c and cache.h two files, including cache Enable, disable, refresh, write back, memory allocation and so on a series of interfaces.

The cache.c file maintains the global structure body variable _g_cacheoplib the various Cache operation interface functions that hold the CPU architecture, that is, from the Arch Layer gets the Cache operation interface function under different architectures .

Cache.cThe file provides a variety ofApiinterfaces, includingApi_cacheenable,Api_cachedisable,Api_cachelock,Api_cacheunlock,Api_cacheflush,Api_cacheflushpage,Api_cacheinvalidate,Api_cacheinvalidatepage,Api_cacheclear,Api_cacheclearpage,Api_cachetextupdate,Api_cachedataupdate,Api_cachelocaltextupdateand other commonly usedCacheThe action function. AllApiinterface implementation of theCacheoperation is done by getting the global struct-body variable_g_cacheoplibThe function pointer member completes the corresponding operation.

2.2      ArchLayerCacheInterface

The BSP program calls the function api_cachelibprimaryinit initialize the Cache system, which is called to the function archcacheinit, and then the PPC The schema invokes the function Ppccacheinit and probes the Cache typeby calling the function ppccacheprobe . the cache probe iterates through the struct array _g_ppccachedrivers and queries the cache type of the PPC architecture thatis already supported in the system . The global struct body variable _g_cacheoplib is initializedfor use by the API layer Cache interface.

3. PPCunder ArchitectureCacheOperational Implementation Analysis

The Cache operation function Code for the PPC architecture in Sylixos is located in the/libsylixos/sylixos/arch/ppc/mm/cache directory, where The Cache driver for the generic PPC architecture is encapsulated in the common directory .

After calling the function Ppccacheprobe, if the Cache type is successfully detected , the struct pointer _g_pcachedriver will point to the specified CPU The Cache driver operating function set for the model number.

similar to The API layer provides various interfaces, andthe ppccache.c file in the common directory also encapsulates a common set of Cache operation functions. These function operations sets provide a true function implementation for each function pointer in the API layer global struct variable _g_cacheoplib .

Sylixos currently implements the PPC series architecture that currently includes the E200,E500 and 60x series.

3.1      E200Series

The E200 series Cache operation function code is located in the/libsylixos/sylixos/arch/ppc/mm/cache/e200 directory, where ppccachee200.c file defines the E200 's Cache drive structure, including Ppce200cacheprobe,__ppce200cachedisable,__ Functions such as Ppce200cacheenable,ppce200dcacheclear,Ppce200dcacheflush, and so on. The specific implementation of each function is located in the assembly file Ppccachee200asm.s .

3.2      E500Series

The E500 series Cache operation function code is located in the/libsylixos/sylixos/arch/ppc/mm/cache/e500 directory, where ppccachee500.c file defines the E500 's Cache drive structure, including Ppce500cacheprobe,ppce500dcachedisable, Ppce500dcacheenable,ppce500icachedisable,ppce500icacheenable, Functions such as Ppce500dcacheflushall, Ppce500dcacheflush, and so on. The specific implementation of each function is located in the assembly file Ppccachee500asm.s .

3.3      60xSeries

60xSeriesCacheThe operation function code is located in/libsylixos/sylixos/arch/ppc/mm/cache/ppc60xdirectory, the currentSylixosin60xSeriesCpuimplementations include603,604,EC603,745,83xx. WhichPpccache603.c,Ppccache604.c,Ppccache745x.c,Ppccache83xx.c,Ppccacheec603.cThe file defines the individualCpuof theCachedrive structure. 60xseries of variousCpuUse the sameCacheinterface, specifically implemented inPpccache60xasm.sin the file. IncludePpc60xicacheenable,Ppc60xdcacheenable,Ppc60xicachedisable,Ppc60xdcachedisable,Ppc60xicacheinvalidate,Ppc60xdcacheclear,Ppc60xdcacheinvalidate,Ppc60xdcacheflushwait for the function.

3.4      Other pending series

Other pending Implementation PPC Series of CPUs, add driver code, you need to add the corresponding series of files in the/libsylixos/sylixos/arch/ppc/mm/cache/directory, in its directory to increase the corresponding . C and . S file, a. C file that defines the Cache action function collection. S file to implement the contents of the Cache operation.

after adding the completion driver, the corresponding driver pointer is added to the struct _g_ppccachedrivers in the ppccache.c file in the common directory , followed by the initialization of this series the Cache function collection of the newly added series can be detected by the CPU .

Sylixos PPC Architecture Series Introduction-cache