Symbian OS hardware-timer

In chapter 5, kernel service, I will explain the use of eka2's millisecond timer. Eka2 uses a 1 millisecond tick timer to drive time shards and timer queues, and tracks wall clock time ).

Generates a regular high-speed timer with 1 millisecond interrupt without drift, and puts forward the minimum hardware requirement. The timer counter must be read/write, and the maximum cycle time must be several seconds long.

The speed of the timer clock source is not important for Symbian OS, but usually between 32 kHz and 1 MHz. The slower the clock source, the less power consumption, and the fast rate clock can improve the timer flexibility in addition to the kernel's millisecond answer (see Figure 2.5 ).

A 32-bit free-running counter combined with a series of 32-bit match registers is the preferred hardware implementation. These matching registers can generate timer interruptions. This implementation allows you to use a simple software solution to solve the problem of jitter resistance and suppress the idle answer and profiling. Automatic re-loading countdown timer is an optional hardware option, but they have little flexibility.

 

Figure 2.5 high-speed timer with three matching registers

 

Common Operations with millisecond timers with matching registers are simple. The external clock source driver counter must check the matching register for each increment. If they match, they will interrupt the line, the millisecond timer ISR will execute, and then the kernel will respond in milliseconds, then ISR adds a 1 ms clock tick to the matching register to requeue the interrupt.

The counter always allows free-running, and the matching register always produces increments on the previous matching value. This process causes a free-drifting millisecond interruption. If the input clock frequency is not an exact multiple of 1Hz, by increasing or removing a small number of additional clock cycles per millisecond interrupt, the anti-jitter software will drive a timer typically 1 ms.

To allow the kernel to precisely track time while the CPU is sleeping, the timer input clock and counter circuit must be powered on from a power source independent of the core.

To debug software running on the high-speed timer system, the JTAG debugger hardware must suspend the timer when the CPU is interrupted. The JTAG debugger enters a debug_halt signal into the timer clock to complete this operation. During single-step debugging, stopping the timer ensures that the OS will not be overwhelmed by the timer interruption, and that the kernel timer queue will not be damaged due to the passage of too many unpredictable times.

Multiple timers are required in the real-time system, even if eka2 only needs one timer. An additional timer is used for peripherals with sub-millisecond-level timing requirements, such as those that do polling for or flash memory. The remaining timers can be used for precise performance analysis.

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Note: This article is translated by bequan from Symbian press's Symbian OS internals: Real-Time Kernal programming book. Anyone who needs to repost or reference, please first contact bequan via email (a-pangu@163.com or symbianchn@gmail.com), can be reposted or referenced after obtaining permission, otherwise it is deemed as infringement. When reprinting or referencing, please indicate the above translation information in the article.