Synchronous timing logic in VERILOGHDL design

Quoted from Professor Xiayu

1. Synchronous timing Logic:

Refers to the value of a register group that represents a state can only be changed when the trigger condition is uniquely determined.

A state machine that can only be triggered by a forward or negative jump along a clock is an example, [email protected] (Posedge CLK).

1.1 Advantages of synchronous timing logic:

Synchronous timing logic is much simpler than asynchronous sequential logic, so we have a rule: using Verilog to design an integrated state machine must use synchronous timing logic.

2. Asynchronous timing Logic:

Refers to the trigger condition has a plurality of control factors, any one factor of the jump can cause the trigger. The clock inputs of the Register group are not all connected to the same clock signal.

For example, the asynchronous timing logic is triggered by using the output of one trigger to connect to the clock end of another trigger.

2.1 Disadvantages of asynchronous timing logic:

1. Because the triggering conditions of asynchronous timing logic are arbitrary, it can happen at any moment.

2. Many integrated amplifiers do not support the synthesis of asynchronous sequential logic

3. Asynchronous timing is difficult to control the risk and competition generated by combinatorial logic and delay.

3. How to ensure clock synchronization:

1) Global network cabling,

2) Adopt a balance tree, and at each level if the buffer,

3) After simulation, reduce the clock frequency

Made by Qidaiymm, your comment is appreciated.

Email:[email protected]

Synchronous timing logic in VERILOGHDL design