PCI bus is a typical tree structure. Taking the host-PCI bridge in the North Bridge as the root, other PCI-PCI bridges in the bus, the PCI-ISA bridge (ISA bus to PCI Bus Bridge) and other bridge equipment and
Devices that directly connect to the PCI bus are considered as nodes. The entire PCI architecture can be summarized as follows:
Through the bridge, PCI can be easily expanded and connected to other bus to form the bus network of the entire system. The bus connected to the HOST-PCI bridge is called Bus 0,
The serial number of another hierarchical bus is determined when the BIOS (or operating system) enumerates the device.
The device identifier can be seen as the address of the device on the PCI bus. Its format is as follows:
The eight-bit bus field represents the bus number of the device, so the system has up to 256 buses. The device field indicates the device number, indicating a device on the bus.
Function indicates the function number, which identifies a function unit (Logical Device) on a specific device ). For example, a PCI Card has two independent devices.
If some electronic lines are shared, these two devices are the two functional units of the PCIe card. As the Function Field Length implies, an independent PCI device can have up to eight functions.
The Unit, device, and function are generally used together to indicate that a total of 256 devices can be deployed on a bus. BDF stands for the device identifier.
PCI configuration space
Programmers do not need to understand the implementation details of the PCI device circuit, but only need to understand its interface. The PCI configuration space is such an interface, and its structure is shown in:
According to the PCI device specification, the configuration space of the device is up to 256 bytes. The format and usage of the first 64 bytes are unified, which is the most important for programmers.
Base address registers and interrupt pin, interrupt line.
(1) base address registers: The base address register, also known as the PCI bar. It reports the device register or device RAM in the I/O port address space
(Or physical address space. The address is dynamically configured by the software (BiOS or operating system. The software (BiOS or operating system) that enumerates the PCI device will
After obtaining all the PCI devices on the platform, assign the I/O port (or physical address) to the PCI bar of each device according to the fixed algorithm based on the number of devices ). Electronic line of the device
Maps these ports (or addresses) to their registers so that the CPU can be accessed through port I/O and physical addresses (mmio ).
To the device. Which access method is used, which is represented by the last bit of the PCI bar. When the bit is 1, it indicates the I/O port; when the bit is 0, it indicates the mmio port.
(2) interrupt pin: interrupt pin. The standard design for PCI disconnection is four: INTA, intb, intc, and intd, corresponding to 0 ~ 3. Value representation of this Register
Which interrupt pin is connected to the device.
(3) interrupt line: the disconnection of the device. This register only provides one protection function, and the bios and operating system can use it freely. BiOS usually uses it to save the device connection
The pin number of the PIC/ioapic.
In X86 architecture, 0xcf8 ~ of the I/O address space ~ The 0xcff segment is reserved for the PCI bus for accessing the configuration space of the device. The first 32-bit register is "Address Register ",
The 32-bit value register is used ". The software writes the BDF of the device and the byte offset of the configuration space to be accessed into the "Address Register" to read and write the configuration space through the "value register.
PCI device enumeration process
The enumeration process of a PCI device is generally completed by the BIOS or the operating system.
From the preceding PCI bus profile, the PCI device and bus constitute a tree structure, where the PCI-PCI bridge is the root node of the subtree, the device enumeration process is to be in the memory
Create a Device Tree that matches the actual bus conditions. The most important step in the enumeration process is the discovery of PCI-PCI bridges. This can be determined by using the headertype field of the PCI configuration space.
If this field is 1, it indicates the bridge device. PCI-PCI bridge has three main attributes:
The following describes the relationship between the three elements.
For PCI-PCI bridge 1, its primary bus is bus 0, secondary bus is Bus 1, and the largest bus in the bus with it as the root, as shown in
So its subordinate bus is Bus 2.
Device enumeration starts from the root node HOST-PCI bridge, first probe each device on bus 0. When the first bridge device is detected, assign it the primary bus number and
Secondary bus number, where secondary bus number is 1 (that is, the most common line number in the current system plus 1), subordinate bus number and secondary bus
When the new bus is found in the subtree, the value is automatically adjusted. Next, take the bridge as the root node and continue to test its subordinate bus. The process is the same as that before, and the first
After the bridge device is mounted, the system continues the probe with its root, so that it repeatedly knows that all the child trees have been detected.
When the PCI-PCI bridge receives the BDF written into 0xcf8, it will match the bus field with its own secondary bus, then it will search for the device on the subordinate bus; if
If the bus value falls within the subordinate bus range, the address is passed to the bridges in the subordinate bus; otherwise, the address is ignored.
In this way, the BIOS or operating system can enumerate all the devices on the bus and allocate resources to them. Once the PCI configuration space is set, the software can use the PCI
Bar directly accesses the device.
System virtualization Study Notes-PCI devices