SystemVerilog parametric classes and their relationship with static __sytemverilog

Two examples of parameterized classes and declarations of static variables are described:

eg

Program Param_stack;
Class Stack # (type T = int);
int m_cnt;
static int counter = 2;

function new;
m_cnt = counter++;
Endfunction:new

Endclass:stack

Class Stacked extends Stack # (real);

Endclass:stacked


typedef stack # (BYTE) stack_byte;
typedef stack # () Stact_int;


Stack_byte S1 = new ();
Stack_byte S2 = new ();
Stack S3 = new ();
Stack # (bit) S4 = new ();
Stacked S5 = new ();


Initial begin
$display ("Counter value of S1 instance =%0d",stack # (BYTE)::Counter);
$display ("Counter value of S2 instance =%0d",stack_byte::Counter);
$display ("Counter value of S3 instance =%0d",Stack # ():: Counter);
$display ("Counter value of S4 instance =%0d", stack# (bit):: Counter);
$display ("Counter value of S5 instance =%0d", stacked::counter);
End

Endprogram:param_stack

The printed values are:

3

4

3

3

3

Explanation: Although a static variable will only have one copy.

Since both S1 and S2 are created by Stack_byte, counter is 3,s2 when S1 is 4;

S3 is created by the default parameter class, equivalent to the Stack_int,counter value in the program is 3;

S4 is created by the type of the bit, and the counter is also 3;

S5.

That is, when the parameters of the parameter classes are not the same, they are different classes.

Note:

you need to be aware of the way parameterized classes refer to static variables .