SystemVerilog use FORCE__SV in class

1. Direct force a value, such as 0/1/a, can be in Class directly force the value of a variable, such as Force Dut.timer=timer, if the timer is a dynamic variable, the compiler will error "class data Is isn't allowed in the non-procedural context. "The simple solution is to define the timer as static Type 3. If the 2 cannot be simply defined as a static type, you can borrow the Interface/bind module to achieve, specifically in the interface to add Trigger/dis-trigger/value three values, in the interface using always block Force dut signal, in class to drive trigger/value/ Dis-trigger

In summary, is the force dut signal on the right side must be a static value