Talk about how to implement Xilinx Microblaze Bootloader

In general, Xilinx Microblaze will be used in the system to do some control classes and simple interface auxiliary work, such as running IIC, SPI, UART and other low-speed interface driver, the FPGA logic function module initialization configuration and do some auxiliary calculation and so on. The code for a class program is generally small, often between more than 10 KB and a KB, so the requirement for storage is usually not too high, and using the FPGA internal RAM resources is sufficient. Then, when Microblaze needs to run the file system, USBHCD, network stack, or even the operating system, the code can be up to a few megabytes or even dozens of MB in size, and the program must run in the external memory. This article takes an example of loading a mirrored image stored in an external qspiflash to an external DDR, and describes the implementation of the Microblaze bootloader.

1.Microblaze Bootloader

Microblaze works the same way as all general-purpose processors, and there's no need to repeat them here. In general, we will combine. Elf code, FPGA bit file, and. IMM RAM initialization file to compose a download.bit file to burn to external flash. Here the Elf executable code becomes the initialization value of the FPGA Block RAM, which can be executed after the reset is released. Presumably this is where we all know. Microblaze bootloader How to do this: in a limited space blockram inside a small piece of code, responsible for initializing the necessary peripherals and the flash inside the other code to carry out the execution of the external memory. This principle is similar to all general-purpose processors, where block RAM is equivalent to an on-chip RAM (OCM) resource for a general-purpose processor such as arm, and this small piece of code is equivalent to the first quarter of bootloader (FSBL).

All of the following examples are validated on Xilinx xc7k325 FPGAs. The development environment is Vivado2015.2. The hardware platform contains a piece of 256Mbit (32M bytes) of Spansion QSPI Flash, a one-piece lux 16bit-wide capacity of 512MB DDR3.

2. Building FPGA hardware

To verify this system, it is necessary to have ①MICROBLAZE②DDR Mig③cache Ram④ interrupt Controller ⑤QSPI Flash IP core ⑥ bus related Axiinterconnect⑦ serial output debugging information and other collaborative work (the project top-level structure see annex).

What you need to specifically note here is the configuration of Qspi Flash, shown in 1. The XIP mode and performace mode of the Axi interface use the Axi full interface to achieve higher bandwidth and ease of use of DMA, using the most basic Axi Lite interface.

Figure 1 QSPI IP Core parameter configuration

Here are two points to note:

①EXT_SPI_CLK: In QSPI mode, the clock's two divide is to give the SPI flash access clock, so this clock to be based on QSPI flash parameters set to a reasonable value;

②startupe2 Primitive: If the external flash hangs on the FPGA's dedicated configuration pin to enable the primitive, the use of ordinary IO can not be enabled.

3. Create Microblaze Bootloader

The following describes how to create Microblaze bootloader in the SDK.

The first step: Create an SPI Flash-based SERC SPI Bootloader, as shown in 2.

Figure 2 Creating the SERC SPI bootloader

The second step: Modify the XILISF library, serial_flash_family=5 select Spansion series Qspi Flash, serial_flash_interface=1 Select Axi interface, shown in 3.

Figure 3 Modifying the XILISF library parameters

Step three: Modify the flash offset for the storage application, as shown in 4.

Figure 4 Modifying the flash offset of a storage application

The FPGA bit file selected by the current example is approximately 10.5MB, so the offset selection is 12MB and needs to be adjusted based on the actual FPGA capacity.

Fourth step: Confirm that the SERC SPI bootloader link script is in the internal RAM space, and the link script that applies the app project points to the external DDR.

So far SERC SPI Bootloader project has been created.

4. Burn and Write Flash

Burn-Write Flash is divided into two parts, one is a bit file, and the other is the application's SERC file.

4.1 Burn Write bit file

To burn a bit file, the first step needs to be the FPGA bit and SERC SPI bootloader elf file synthesis, 5, click Programming, the default composition of the file named Download.bit. If you are good at using the command line, you can also generate it manually using the Updatemem command.

Figure 5 Programming bit file generation

The second step is to burn write generated download.bit file to Flash, here no longer say, note that flash offset address is 0x00.

4.2 Burn Write application Serc

In fact, the application burning Flash is the Serc file, the file can be burned to write to a special offset position. 6, if you need to write with another tool, you can also use the command mb-objcopy to manually convert the. elf file to the Serc file.

Figure 6 Burning the application to a specific offset address

5. Summary

Microblaze bootloader is necessary in the system of Microblaze running large and medium-sized software, hope this article can play a role. If you have any questions or comments can join QQ discussion group 300148644 communication.

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Talk about how to implement Xilinx Microblaze Bootloader