Talking about SPI Bus

The Serial Peripherals Interface (serial peripheral INTERFACE,SPI) is developed by Motorola to provide a low-cost, Easy-to-use interface between microcontrollers and peripheral chips (SPI is sometimes referred to as a 4-line interface). This interface can be used to connect memory, Ad/da converters, real-time clock calendars, LCD drives, sensors, audio chips, and even other processors. Currently, there are many components that support the SPI, and they are increasing.
　　
Here you need to mention, since patents are critical in the electronics industry, some manufacturers may rename the SPI protocol to avoid high royalties, but the hardware is handled the same way, except for a different name (or some modification of the protocol), such as TI's SSI (synchronous Serial Interface) communication protocol.
　　
Unlike a standard serial port, the SPI is a synchronous protocol interface in which all transmissions refer to a common clock, which is generated by the host (processor). The device that receives the data (from the device) uses the clock to synchronize the reception of the serial bit stream. There may be a number of chips connected to the same SPI interface on the host, which is the host that chooses to receive data from the device by triggering the selection of input pins from the chip of the device, and no selected peripherals will participate in the SPI transmission.
　　
SPI mainly uses 4 signals: Host output/input from machine (Mosi), host input/output from machine (MISO), Serial clock (SCLKOrSCK) and peripheral tablet selection (NCS）。 Some processors have a special slice selection for the SPI interface, called the Machine selection (NSS）。
　　
The MOSI signal is generated by the host and received from the machine. On some chips, Mosi is simply marked as serial input (SI), or serial data input (SDI). The MISO signal is generated from the machine, but it is still under the control of the host. On some chips, MISO is sometimes referred to as serial output (so), or serial data output (SDO). Peripheral chip selection signals are usually only generated by the standby I/O pins of the host.
　　
SPI interface in the internal hardware is actually two simple shift registers, in the main device shift pulse, data by bit, high in front, low after, for full-duplex communication, data transmission speed overall than the I2C bus faster, the speed can reach the Mbps level.

SPI has four working modes , depending on clock polarity and clock phase.
　　
Clock polarity has high and low poles:
1, the clock low electricity peacetime, the idle Time Clock (SCK) at the low level, transmits jumps to the high level;
2, the clock polarity for high electricity peacetime, idle clock at a high level, transfer to a low level.

There are two clock phases: Phase 0 and Phase 1. For clock phase 0, if the clock polarity is low, the MOSI and MISO outputs are valid on the rising edge of the Clock (SCK) (as shown in Figure 1).

Figure 1. SPI sequence diagram with clock polarity of low level and clock phase 0 o'clock
If the clock polarity is high, for clock phase 0, these outputs are valid in the SCK descent (shown in Figure 2).

Figure 2. SPI sequence diagram with clock polarity of high level and clock phase 0 o'clock
For clock Phase 1, the opposite is true. At this point if the clock polarity is low, the Mosi and MISO outputs in the clock (SCK) fall along effectively (as shown in Figure 3).

Figure 3. SPI sequence diagram with clock polarity of low level and clock phase 1 o'clock
If the clock polarity is high, these outputs are valid in the ascent of the SCK (as shown in Figure 4).

Figure 4. SPI sequence diagram with clock polarity of high level and clock phase 1 o'clock

In the engineering generally will use the Cpol to represent the clock polarity, uses the Cpha to represent the clock phase, in s5pv210 datasheet, we can see the corresponding SPI interface configuration register (as shown in Figure 5).

Figure 5. s5pv210 SPI Configuration Register CH_CFGN

That is, two bits (Cpol and Cpha) together determine the working mode of the SPI, so there are 2 * 2 = 4 working modes. The clock polarity (CPOL) determines the high and low state of the clock when it is idle (0: Idle Low level, 1: Idle high level); the clock phase (Cpha) determines that the data in the clock's ascent along or down along the latch/sample (0: The first edge begins, 1: The second edge begins).
Finally, one disadvantage of the SPI interface is that there is no flow control specified and no answer mechanism to confirm whether or not to receive the data.