The task and function in the SV do not need to be added with a begin. End to indicate the body.
Task Muliple_line;
... the body ...
Endtask:multiple_line
The subroutine returns when it executes to the last line of the subroutine, assigns the return value to a variable with the same name as the function, or it can call return explicitly.
The sub-programs of module and program in SV are stored statically by default, and when dynamic storage is required, it is still necessary to explicitly indicate with automatic explicitly. (Automatic is the default in class)
The default value for the parameter in the subroutine is logic input. Verilog sub-program parameter processing is, when entering the subroutine, input and inout values are assigned to the subroutine local variables, when the subroutine returns the output and
The value of the inout is assigned to the variable in the module. The SV adds a way to ref, which is specified as a reference instead of a copy. This method can only be used in automatic subroutines, the advantage of which is in the subroutine
Modify the variable to swap with its module is always visible.
Task Bus_read (input logic [31:0] addr, ref logic [31:0]data); Initial fork
bus.request = 1 ' b1; bus_read (addr,data);
@ (Posedge bus.grant) BUS.ADDR =addr; thread2: begin //uses the ref type to pass data, which does not require the
@ (Posedge bus.enable) data = bus.data; @data //to wait until the bus_read process finishes,
....... $display; Thread2 can see the change of data
endtask:bus_read end
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Task and function in SV