TE2440II-bootloader-option.inc

; This file is included by 2440init. S (get option. Inc)

This option. inc file is mainly used to set the clock service and select the frequency division coefficient. Including (CPU selection, Crystal Oscillator Selection, fclk, hclk, pclk)

 

 

 

 

 

 

; ========================================================== ===
; Name: option.
; Desc: configuration options for. s files
; History:
; 02.28.2002: ver 0.0
; 03.11.2003: ver 0.0 attached for 2440.
Jan E, 2004: ver0.03 modified for 2440a01.
; ========================================================== ===

; Start address of each stacks,
_ Stack_baseaddress equ 0x33ff8000
_ Mmutt_startaddress equ 0x33ff8000
_ Isr_startaddress equ 0x33ffff00

Gbll pll_on_start; declare a logical variable and initialize it to false
Pll_on_start SETl {true}; start the phase-locked loop at the beginning

Gbll endian_change
Endian_change SETl {false}

Gbla entry_bus_width; why is entry_bus_width 16? What is this?
Entry_bus_width Seta 16

; Buswidth = 16, 32
Gbla buswidth; max. bus width for the gpio Configuration
Buswidth Seta 32; what is the purpose?

Gbla uclk
Uclk Seta 96000000; 48000000

Gbla xtal_sel; Crystal Oscillator variable
Gbla fclk; CPU clock
Gbla cpu_sel; CPU Selection

; (1) Select CPU
Cpu_sel Seta 32440000; 32440000: 2440x.
Cpu_sel Seta 32440001; 32440001: 2440a

; (2) Select xtal
Xtal_sel Seta 12000000
. Xtal_sel Seta 16934400

; (3) Select fclk
; Fclk Seta 296352000
; Fclk Seta 271500000
; Fclk Seta 100000000
Fclk Seta 240000000
Fclk Seta 280000000
Fclk Seta 320000000
Fclk Seta 360000000
Fclk Seta 400000000; fclk is set to 400 m

; (4) Select clock Division (fclk: hclk: pclk)
; Clkdiv_val equ 5; 0 =, 1 =, 2 =, 3 =, 4 =, 5 =, 6 =, 7 =.

[Xtal_sel = 12000000
 
[Fclk = 271500000
Clkdiv_val equ 7;
M_mdiv equ 173; fin = 12.0 MHz fout = 271.5 MHz
M_pdiv equ 2
[Cpu_sel = 32440001
M_sdiv equ 2; 2440a
|
M_sdiv equ 1; 2440x
]
]
 
[Fclk = 100000000
Clkdiv_val equ 0;
M_mdiv equ 42; fin = 12.0 MHz fout = 100 MHz
M_pdiv equ 4
[Cpu_sel = 32440001
M_sdiv equ 1; 2440a
|
M_sdiv equ 0; 2440x
]
]

[Fclk = 240000000
Clkdiv_val equ 4;
M_mdiv equ 112; fin = 12.0 MHz fout = 240 MHz
M_pdiv equ 4
[Cpu_sel = 32440001
M_sdiv equ 1; 2440a
|
M_sdiv equ 0; 2440x
]
]
 
[Fclk = 280000000
Clkdiv_val equ 4;
M_mdiv equ 132; fin = 12.0 MHz fout = 280 MHz
M_pdiv equ 4
[Cpu_sel = 32440001
M_sdiv equ 1; 2440a
|
M_sdiv equ 0; 2440x
]
]
 
[Fclk = 320000000
Clkdiv_val equ 5;
M_mdiv equ 72; fin = 12.0 MHz fout = 320 MHz
M_pdiv equ 1
[Cpu_sel = 32440001
M_sdiv equ 1; 2440a
|
M_sdiv equ 0; 2440x
]
]
 
[Fclk = 360000000
Clkdiv_val equ 5;
M_mdiv equ 82; fin = 12.0 MHz fout = 360 MHz
M_pdiv equ 1
[Cpu_sel = 32440001
M_sdiv equ 1; 2440a
|
M_sdiv equ 0; 2440x
]
]

[Fclk = 400000000
Clkdiv_val equ 5;
M_mdiv equ 127; 127
M_pdiv equ 2; 2
[Cpu_sel = 32440001
M_sdiv equ 1; 2440a
|
M_sdiv equ 0; 2440x
]
]
 
[Uclk = 48000000)
U_mdiv equ 56; fin = 12.0 MHz fout = 48 MHz
U_pdiv equ 2
[Cpu_sel = 32440001
U_sdiv equ 2; 2440a
|
U_sdiv equ 1; 2440x
]
]
[Uclk = 96000000)
U_mdiv equ 56; fin = 12.0 MHz fout = 96 MHz
U_pdiv equ 2
[Cpu_sel = 32440001
U_sdiv equ 1; 2440a
|
U_sdiv equ 0; 2440x
]

]

|; Else if xtal_sel = 16.9344 MHz

[Fclk = 266716800
M_mdiv equ 118; fin = 16.9344 MHz
M_pdiv equ 2
[Cpu_sel = 32440001
M_sdiv equ 2; 2440a
|
M_sdiv equ 1; 2440x
]
]
 
[Fclk = 296352000
M_mdiv equ 97; fin = 16.9344 MHz
M_pdiv equ 1
[Cpu_sel = 32440001
M_sdiv equ 2; 2440a
|
M_sdiv equ 1; 2440x
]
]
[Fclk = 541900800
M_mdiv equ 120; fin = 16.9344 MHz
M_pdiv equ 2
[Cpu_sel = 32440001
M_sdiv equ 1; 2440a
|
M_sdiv equ 0; 2440x
]
]
 
[Uclk = 48000000)
U_mdiv equ 60; fin = 16.9344 MHz fout = 48 MHz
U_pdiv equ 4
[Cpu_sel = 32440001
U_sdiv equ 2; 2440a
|
U_sdiv equ 1; 2440x
]
]
[Uclk = 96000000)
U_mdiv equ 60; fin = 16.9344 MHz fout = 96 MHz
U_pdiv equ 4
[Cpu_sel = 32440001
U_sdiv equ 1; 2440a
|
U_sdiv equ 0; 2440x
]
]
 
]; End of 'if xtal_sel = 12000000.