Tell me about timing (reprint)

This article original location: Fpganotes Blog

Http://wiki.fpganotes.com/doku.php/ise:timing:my_summary

Intro

Q: What criteria should be used to test an FPGA design project?

1. The function is correct;
2. Timing closure;
3. Low resource consumption.

Timing convergence, that is, timing Closure, means that the design of the various timing indicators can meet the requirements set before the design. Therefore, the whole process is divided into two parts:

1. Develop timing requirements
2. Meet timing requirements

Timing Constraints Classes

Timing requirements are usually determined by the external environment of the entire system circuit, such as:

• How fast is the clock speed provided to the FPGA by the entire circuit system
• Whether the FPGA input data is a synchronous signal or an asynchronous signal and its frequency
• Frequency required for FPGA output data
• Phase relationship of input/output data to clock

Summing up the above-mentioned various requirements, the FPGA chip external three kinds of timing constraints:

• Period (Clock period constraint): Constrains the minimum clock frequency that can be used by the same clock-driven register (or synchronous device) to ensure the sampling time and hold time of the FPGA internal synchronization signal.
• Offset: Constrains the clock-to-data phase difference with clock-sampled data (offset in) or clock-out data (offset out) to ensure that FPGA sampling data is established and the next-level chip gets the sampled time of the data.
• Pad to pad: when the input data into the FPGA did not go through any synchronization device (that is, clock-driven devices such as registers, Bram, etc.), only after the combination of logic on the output sheet, pad to pad of the From ... To.. Constraints are used to guarantee the internal delay time.

With the above three constraint types, you can describe any possible conditions for the outside world, and clearly explain the timing requirements that the final design needs to meet, and the FPGA implementation tool will route the layout according to this requirement and try to meet the requirements. Xilinx has a number of documents explaining how to write timing constraints. One thing to emphasize here is that timing constraints are first a reflection of the external environment, followed by the requirements for the layout and routing tools. Timing constraints explain to the tool how the signals from the upstream device are, what input the downstream devices require, and how the FPGA implementation tools are integrated, laid out, routed, and the timing closure design is likely to work properly in a real circuit environment.

Timing Constraint File

Here is a myth that needs clarification: most people think that timing constraints are written in UCF files, in fact, the timing constraints in UCF only work in the layout and routing process. In order to achieve the best timing performance, we should use constraints from the beginning of the synthesis. You can add timing constraints whether it's Xilinx XST, synplify, or other integrated tools. Adding timing constraints during the synthesis process makes it possible for the integrated device to synthesize the appropriate grid tables, making it easier to meet timing requirements when laying out a layout.

Debug

Design timing convergence usually has the following phenomena:

• Par reports cabling complete, but with timing error;
• Par reports that the layout and routing are stopped because of the impossibility of timing closure;
• Timing Analyzer report shows that the design of the Timing score is not 0;
• The FPGA does not work properly at a given clock rate on the actual board and reduces the clock rate the FPGA works fine

If the clock rate is lowered to make the FPGA work properly, and the timing report does not show timing errors, there is sufficient reason to suspect that the timing constraints are not fully constrained to all on-chip paths, and that the entire design needs to be carefully researched and fully constrained.

So how do we solve the timing error in the design? The simplest, the two eyes a smear, let the tool solve: the map, par and other tools effor level refers to the highest, but usually the result of the Ascension is not obvious. We need to selectively use different approaches to different situations. Here are some common scenarios to analyze:

Timing report shows a particular section of net route delay is particularly long

This net is found in the FPGA cross probing. If the input and output distance is really long, then because of the place problem, to solve the place problem, you need to check why the tool will put two lut/ff so far, is the related logical layout problem, or because pin locking causes the problem of unable to move logic.

A common workaround is to perform a copy register operation on the pre-register. Refer to Xilinx AR9410.

If the register cannot be moved due to a register of input/output connections being pack to IOB, you can use the Iob=false constraint to place the register in slice logic.

The timing report shows that there are more logical hierarchies, and that there are no extra-long delays in these levels

If you have too many lut-to-lut levels, you can first use the XST Register balancing feature. If this is not enough, you may need to manually adjust the composition logic, insert a register in the middle, and modify other related code to make the relevant data latency consistent. Other methods refer to Xilinx AR9417.

If the carry chain is too long, consider using a two smaller counter/adder cascade. When taking into account that the carry logic is arranged vertically, when a column is exceeded, the rounding causes the delay to become much longer, and the length of the carry chain is more important.

If the delay is longer for Bram to subsequent FF, consider several scenarios:

• The output of the Bram drives the FF directly, and the target frequency is higher, such as 400-500mhz. To reduce this TCO delay from Bram to FF, you should use the Bram primitive internal register
• The output of the Bram is driven by some combination logic to drive the FF, and the target frequency is relatively low, <300mhz. In order to remove the Bram TCO from this path, you should select the output register in the core without primitive when generating Bram with Coregen.
• If the target frequency is high and the Bram output goes through the Lut drive FF again, then the registers in the primitive and core are best used. This reduces TCO and alleviates the timing requirements of subsequent logic.

Refer to Xilinx AR9412.

Hold violation

Hold violation are usually caused by gated clock. The gating clock is not used in the check design. Gated clocks are typically generated by a counter divider. Use the clock resources provided by the FPGA as much as possible, using DCM as Deskew.

Offset constraint not satisfied

The first thing to do is to ensure that offset is written correctly.

Then ensure that the input/output data into the FPGA in the register with a beat, the middle do not add the combination of logic. Register pack to IOB to ensure that the offset constraint is met to the maximum extent possible. (Similarly, as mentioned above, not placing registers in the IOB will be advantageous for period constraints.) ）

If you are not satisfied, you may need to adjust the phase of the clock and the data. You can use DCM Phase shift to adjust the clock phase or idelay to adjust the data phase.

A set of buses can be intentionally arranged in the internal IOB position at the time of pinout, the lower effective bit is below, the high effective bit is above, rather than by the position of the external pinout.

If all of the above methods are used and a little bit less than the target, then you can try to use some of the properties of the tool, such as:

Map   * Timing driven Packing  * Effort level, Extra Effort  * Global optimization  * Allow Logic Optimize Acro SS Hierarchy  * combinational Logic optimization  * Cost tablepar   * Effort level  * Extra Effort

You can also use MPPR or Xplorer to run multiple times to pick the best results.

If all attempts fail to meet the previously established timing goals, it may be time to reconsider whether the goal is justified.

Tell me about timing (reprint)