Test the mini2440 bare metal -- direct DMA access for UART (Serial Port) Communication

This can only be used as an example for your initial understanding of MDA.

Functions:

Pass the string data to utxh0 through the dma0 channel, and then

Display. After data transmission, dma0 is interrupted, beep sound, and LED light.

 

Basic DMA knowledge

Common Data Input/Output Methods in computer systems include query methods (including unconditional and conditional transmission methods) and interrupt methods, which are suitable for data exchange between CPU and low-speed and medium-speed peripherals. However, when high-speed peripherals need to transfer a large amount of data quickly between the system memory or different areas of the system memory, the data transmission rate is limited to a certain extent. Direct Memory Access (DMA) is proposed to solve this problem. In the DMA mode, the DMA controller replaces the CPU in a certain period of time to obtain control of the bus, to implement fast transmission of large amounts of data between memory and peripherals or different areas of memory.

 

DMA Overview:

Sc2440 supports four-channel DMA control between the system bus and the peripheral bus. The DMA of each channel can handle four situations:

1. Both source and target devices can be deployed on the system bus.

2. The source device is on the system bus and the target device is on the peripheral bus.

3. The source device is on the peripheral bus while the target device is on the system bus

4. Both source and target devices can be deployed on the peripheral bus.

The biggest advantage of DMA is that it can transmit data without CPU interference. You can use software to control DMA startup, or use internal or external request pins.

 

DMA Control

DMA uses a three-state Finite State Machine (FSM) to control it, which is described in the following three steps:

Status 1:

In the initial status, the DMA waits for the DMA request. When the DMA request arrives, it enters status 2. In this phase, the DMA ack and INT req are both 0.

 

Status 2:

In this phase, the DMA ack becomes 1 and the counter curr_tc loads data from the dcon [] register. (Note: The DMA ack remains 1 until it is cleared)

 

Status 3:

In this phase, DMA initializes sub-FSM that performs atomic operations (atomic operation. Sub-FSM reads data from the source address and writes the data to the target address. Before this operation, the data size and transmission size should be considered. Before the value of the counter (curr_tc) in the whole mode is 0, data transmission continues. After sub-FSM completes the atomic operation, the primary FSM performs a countdown. In addition, when the counter crrr_tc is set to 0 and the dcon [29] register is set to 1, the primary FSM sends an int req signal. In addition, the DMA Ack is also cleared.

 

DMA register Configuration

Rdisrc0 = (u32) sendbuffer; // data address rdisrcc0 | = (0 <1) | (0 <0); // [1] system bus, [0] The address increases rdidst0 = (u32) utxh0 based on the data size after each transmission in single and burst modes; // the destination address utxh0 {2440addr. # define utxh0 (0x50000020)} rdidstc0 | = (0 <2) | (1 <1) | (1 <0 )); // [2] an interruption occurs when the TC reaches 0. [1] APB (on the peripheral bus), [0] The address bus remains unchanged after transmission. // instructions on the above registers, rdisrc0 and rdidst0 are respectively configured as the data address (inside the DMA), transmission target address (UART is a peripheral device), and rdisrcc0 and rdidstc0 rdcon0 |=( (u32) 1 <31) | (0 <30) | (1 <29) | (0 <28) | (0 <27) | (1 <24) | (1 <23) | (1 <22) | (0 <20) | (15); // [31] handshake mode; [30] synchronous pclk = 50 m (APB clock <peripherals>); [29] An Interrupted request is generated when all transmission is completed (that is, curr_tc is changed to 0 ); [28] perform a unit transmission. // [27] select the single service mode in which the DMA stops and waits for other DMA requests after each atomic transmission (single or sudden 4; [24] uart0; [23] Select a DMA source to trigger the DMA Operation; // [22] when the current value of the transfer count changes to 0, the DMA channel (DMA req) is disabled; [20] bytes (transmitted in one byte each time); [] initial transfer count: 15 ,15 = length of the sendbuffer character array; rdmasktrig0 = (0 <2) | (1 <1) | (0 <0); // [1] Open the DMA channel and process the DMA request of this channel

Summary

Source Address: the address of the string sendbuffer

Destination Address: uart0 address

MDA is only a mechanism for data transmission and serves as a bridge.

The value assignment of the MDA string sendbuffer is not implemented here, but is completed by the CPU. The MDA is transmitted directly from the memory (the string has been stored in the memory by the CPU) to uart0, and the string Hello mini2440 !, 15 characters in length, one byte is output each time, and 15 times is output. TC is the number of output records. Each output time, TC is reduced by 1, and the value is 0, one-service mode for stopping DMA and waiting for other DMA requests. If an interrupt is set, the MDA is interrupted. Therefore, TC is the cycle.

Code Area

Main. c

# Define global_clk 1 # include "def. H "# include" option. H "# include" 2440addr. H "# include" 2440lib. H "// function declaration # include" 2440slib. H "# include" MMU. H "# include" profile. H "// extern void dma_uart (void); void main (void) {u32 mpll_val = 0, consolenum; port_init (); mpll_val = (92 <12) | (1 <4) | (1); // init fclk = 400 m, changempllvalue (mpll_val> 12) & 0xff, (mpll_val> 4) & 0x3f, mpll_val & 3); changeclockdivider (14, 12); // The result of rclkdivn [0: 1: 0: 1] 3-0 bit cal_cpu_bus_clk (); /hclk = 100 m pclk = 50 m consolenum = 0; // UART 1 select for debug. uart_init (2000,100); uart_select (consolenum); mmu_init (); // interrupt ing address initialization BEEP (); dma_uart (); // realize UART (Serial Port) Communication in DMA mode}

Dma_uart.c

// ================================================ ==============================================/// Implement functions: // direct DMA access for UART (Serial Port) Communication, // transmit string data to utxh0 through dma0 channel, and then display it on the terminal. After data transmission, dma0 is interrupted, beep sound, and LED light. //: Liang huiyong // ========================================== ================================= # include "2440addr. H "# include" 2440lib. H "// beep function char * sendbuffer =" Hello mini2440! "; // Source data /*********************************** * ************************** DMA initialization *********** **************************************** * **********/void dma_init () {rdisrc0 = (u32) sendbuffer; // data address rdisrcc0 | = (0 <1) | (0 <0); // [1] system bus, [0] The address increases rdidst0 = (u32) utxh0 based on the data size after each transmission in single and burst modes; // the destination address utxh0 {2440addr. # define utxh0 (0x50000020)} rdidstc0 | = (0 <2) | (1 <1) | (1 <0 )); // [2] an interruption occurs when TC reaches 0 ,[ 1] APB (on the peripheral bus), [0] The address bus remains unchanged after transmission // For the above register description, rdisrc0 and rdidst0 are configured as data addresses (inside the DMA) respectively) transmission target address (UART is a peripheral device), and then configure rdisrcc0 and rdidstc0 rdcon0 |=( (u32) 1 <31) | (0 <30) | (1 <29) | (0 <28) | (0 <27) | (1 <24) | (1 <23) | (1 <22) | (0 <20) | (15); // [31] handshake mode; [30] synchronous pclk = 50 m (APB clock <peripherals>); [29] An Interrupted request is generated when all transmission is completed (that is, curr_tc is changed to 0 ); [28] perform a unit transmission. // [27] select the single service mode in which the DMA stops and waits for other DMA requests after each atomic transmission (single or sudden 4; [24] uart0; [23] Select a DMA source to trigger the DMA Operation; // [22] when the current value of the transfer count changes to 0, the DMA channel (DMA REQ) Disabled; [20] bytes (transmitted in one byte at a time); [] initial transfer count: 15, 15 = length of the sendbuffer character array; rdmasktrig0 = (0 <2) | (1 <1) | (0 <0 ); // [1] Open the DMA channel and process the DMA request }/************************ * ************************************ DMA interruption **************************************** * *******************/void _ IRQ dma0_isr () {rsrcpnd | = 0x1 <17; // clear the suspension rintpnd | = 0x1 <17; uart_printf ("\ n *** DMA to UART finished *** \ n"); BEEP (2000,100); rgpbcon = 0x0154 00; rgpbdat = 0x6 <5 ;} /*************************************** * ******************** | DMA subfunction | set 2440lib. in C, rucon0 | = (1 <0) | (1 <3) | (2 <10 )); **************************************** * ********************/void dma_uart () {uart_printf ("\ n *** Hello DMA to UART *** \ n"); delay (1000); dma_init (); // DMA initializes rintmsk & = ~ (1 <17); // enable dma0 to interrupt pisr_dma0 = (u32) dma0_isr; while (1 ){}}

Complete Project

Test the mini2440 bare metal -- direct DMA access for UART (Serial Port) Communication