The design of the divider using the OpenGL

Recently, due to the Task Arrangement of the lab teacher, I re-checked the implementation of the divider using the Tilde language (OpenGL). The summary is as follows, to be viewed later (the focus is to check which clk_out counter is used to flip the status)

1. The even division duty cycle is 50%

In essence, it is implemented by an n counter module. First, there must be a reset signal. This reset signal is used to make the counter and the output clk_out have a reset value at the beginning, the second is the count flip. Note which value is counted as the flip. First, when the reset is reset, the initial counter value is 0, then, when the counter is counted to n/2-1, the CLK-out status is flipped, that is, clk_out <= ~ Clk_out, at this time do not forget the counter plus 1 operation (count <= count + 1), followed by the counter to the N-1 clk_out and then flip the status, at the same time the counter is cleared. Count <= 0;

The code for this part of the program is as follows:

Module tmm_c (CLK, reset, M, clk_out );
Input CLK;
Input reset;
Input [7: 0] m;

Output clk_out;

Reg [7:0] count;
Reg clk_out;

[Email protected] (posedge CLK)
Begin
If (reset)
Begin
Count <= 0;
Clk_out <= 0;
End

Else
If (COUNT = m-1)
Begin
Clk_out <= ~ Clk_out;
Count <= 0;
End
Else
If (COUNT = m/2-1)
Begin
Clk_out <= ~ Clk_out;
Count <= count + 1;
End
Else
Count <= count + 1;
End

Endmodule

The related testbench code is as follows:

'Timescale 1ns/1ns
Module tmm_c_tb;
Reg CLK;
Reg reset;
Reg [7:0] m;
Wire clk_out;

Tmm_c U1 (CLK, reset, M, clk_out );

Initial
Begin
CLK = 0;
Reset = 1;
M = 4;
#10 reset = 0;
#1000 $ stop;
End
Always #5 CLK = ~ CLK;

Endmodule

Modelsim simulation waveform:

 

2. The odd division duty cycle is 50%.

Actually, it is a counter. The idea is similar to that of an even number. However, two always modules are required in the early stage of odd number division. The output of these two always modules is clk_out1 and clk_out2 respectively, and two count1 and count2 are used, among them, the output of clk_out1 is the result of counting output triggered by the rising edge of the clock to be divided. This also requires the counter module and the reset signal. But what is the value of clk_out1 during this time? After reset, the output and count are all zero, and then clk_out1 is flipped when Count = (N-1)/2, counting to Count = N-1 when the counter is cleared, clk_out is flipped. The counter and output of clk_out2 are the same as those of count1 and clk_out1, but the difference is that it is triggered at the descent edge of the clock to be divided. The most general result is clk_out = clk_out1 | clk_out2 (OR)

The following is the program code:

Module tnn_c (CLK, reset, N, clk_out );
Input CLK;
Input reset;
Input [7: 0] N;
Output clk_out;

Reg [7:0] count1;
Reg [7:0] count2;
// Reg clk_out;
Reg clk1;
Reg clk2;

[Email protected] (posedge CLK)
Begin
If (reset)
Begin
Count1 <= 0;
Clk1 <= 0;
End
Else
If (count1 = N-1)
Begin
Count1 <= 0;
Clk1 = ~ Clk1;
End

Else
If (count1 = (n-1)/2)
Begin
Clk1 = ~ Clk1;
Count1 <= count1 + 1;
End
Else
Count1 <= count1 + 1;

End

[Email protected] (negedge CLK)
Begin
If (reset)
Begin
Count2 <= 0;
Clk2 <= 0;
End
Else
If (count2 = N-1)
Begin
Count2 <= 0;
Clk2 = ~ Clk2;
End
Else
If (count2 = (n-1)/2)
Begin
Clk2 = ~ Clk2;
Count2 <= count2 + 1;
End
Else
Count2 <= count2 + 1;

End

Assign clk_out = clk1 | clk2;

Endmodule

Corresponding testbench:

'Timescale 1ns/1ns
Module tnn_c_tb;
Reg CLK;
Reg reset;
Reg [7:0] N;
Wire clk_out;

Tnn_c U (CLK, reset, N, clk_out );

Initial
Begin
CLK = 0;
Reset = 1;
N = 5;
#30 reset = 0;
#1000 $ stop;
End
Always #5 CLK = ~ CLK;

Endmodule

Modelsim simulation diagram: