The difference between ARM7 and Cortex M3

Comparison of CORTEX-M3 and ARM7

In March 2005, ARM announced the latest ARMV7 architecture and defined three major series:

the "A" series is designed for cutting-edge virtual memory-based operating systems and user applications. Mainly for the growing running of consumer electronics and wireless products including Linux, Windows CE and Symbian;

The "R" series is for real-time systems. Mainly for systems that need to run real-time operating systems for control applications, including cycling electronics, networking and imaging systems.

the "M" series offers optimizations for microcontrollers and low-cost applications. An embedded application that is sensitive to development costs while increasing performance requirements, such as microcontrollers, bike body control systems and a variety of large appliances.

Compare items	ARM7	Cortex-m3
Architecture	ARMV4T (von Neumann) instruction and data bus are common, bottlenecks occur	ARMV7-M (Harvard) instruction and data bus separate, no bottleneck
Instruction Set	32-bit ARM instruction + 16-bit thumb instruction A state switch is required between two sets of instructions	THUMB/THUMB-2 instruction set 16-bit and 32-bit instructions can be directly mixed without state switching
Pipeline	3-Stage Pipeline if there is a transfer need to refresh the pipeline, heavy losses	3-Stage Pipeline + branch prediction The pipeline does not need to be refreshed when the transfer occurs, almost no loss
Performance	0.95dmips/mhz (ARM mode)	1.25dmips/mhz
Power	0.28mw/mhz	0.19mw/mhz
Low power mode	No	Built-in sleep mode
Area	0.62MM2 (kernel only)	0.86MM2 (core + peripherals)
Interrupt	Normal interrupt IRQ and fast interrupt Fiq too few, many peripherals have to be reused interrupt	Non-shielded interrupt nmi+1-240 physical interrupts each peripheral can have an exclusive interrupt, high efficiency
Interrupt delay	24-42 clock Cycles, slow	12 clock cycles, as fast as 6
Interrupt pressure Stack	Software manual stacking, long code and low efficiency	Hardware Auto-stack, no code and high efficiency
Memory protection	No	8-Segment Memory Protection Unit (MPU)
Kernel Registers	Registers are divided into multiple groups, complex structure, more than the nuclear area	Register not grouped (except SP), simple structure
Working mode	7 modes of operation, more complex	Only two types of threading mode and processing mode, simple
Multiplication Law Directive	Multi-cycle multiplication instruction, no division instruction	Single-cycle multiplication instruction, 2-12-period Division Instruction
-bit operation	No access peripheral register requires "read-change-write" 3 steps.	Advanced Bit-band-bit operation technology for direct access to a value of peripheral registers
System beat Timing	No	Built-in System beat timer facilitates OS porting

The difference between ARM7 and Cortex M3