The difference between parameter and define in Verilog

1. Grammar

Statement:

Parameter data = 8 ' D14;

' Define Data 8 ' D14

Use:
Data

' Data

2. Scope

Parameter the file that acts on the Declaration, ' define reads from the compiler until the end of the compilation is valid, or the ' undef command invalidates it.

If you want parameter or ' define to work on the entire project, you can write the following declaration in a separate file and use ' include to have each file contain a declaration file:

' ifndef data

' Define data 8 ' D14

Or

parameter data = 8 ' D14;

' endif

' Define can also be written at the top of the file that the compiler compiles first. The compiler can usually define the compilation order or start compiling from the bottommost module. So write it down at the bottom.

3. Difference

The parameter can be used as a parameter pass at the time of the instantiate.

The difference is quite large when using the state machine. The definition of a state machine can be defined with parameter, but it is not recommended to use the ' Define macro definition because the ' Define macro definition automatically replaces the macro defined in the entire design at compile time, and parameter only defines the parameters inside the module. The defined parameters are not confused with other state machines outside the module. For example, in a project there are two module each containing an FSM, if the design has the state of the name idle, if the use of ' Define macro definition will be confused, if the use of parameter will not cause any adverse effects.

Once the ' define instruction is compiled, it is valid throughout the compilation process. For example, a defined constant can be called in another file by using the ' define directive ' in the other file. Until it encounters ' undef;parameter only valid in the defined file, it is not valid in other files.