The difference between parameter (parameter) and define (macro definition) in Verilog

The difference between parameter (parameter) and define (macro definition) in Verilog

1. Statement format

Parameter xx=yy; (with semicolons)

' Define XX yy (no semicolon)

1. Function range

The parameter is local and works only within the module that it defines, and the macro definition works on multiple files that are compiled at the same time. Even if a macro definition is specified inside a module, it still works on multiple files during compilation until it encounters a redefinition.

1. In the state machine environment

The definition of a state machine can be defined with parameter, but it is not recommended to use the ' Define macro definition because the ' Define macro definition automatically replaces the macro defined in the entire design at compile time, and parameter only defines the parameters inside the module. The defined parameters are not confused with other state machines outside the module. For example, in a project there are two module each containing an FSM, if the design has the state of the name idle, if the use of ' Define macro definition will be confused, if the use of parameter will not cause any adverse effects.

The difference between parameter (parameter) and define (macro definition) in Verilog