The difference between the full-phase mappings between cache and main memory, direct mappings and group-linked mappings

2017-02-22

Note: This article is not original, from Baidu Library, just feel better written, so share. If someone's intellectual property, hope to tell! Thank you

1. function, structure and working principle of high-speed buffer memory

Buffer memory is a primary memory that exists between main memory and CPU, which consists of a static memory chip (SRAM), which is smaller but much higher than main memory, and is close to the CPU speed. The function of the cache is to store the commands and data that need to be run in the near future. The goal is to increase CPU access to the memory. 2 technical problems need to be solved: one is the image and conversion of main memory address and cache address, and the other is to replace the contents of the cache according to certain principle. The structure and working principle of the cache are shown in 2.3.1.

Mainly consists of three major parts:

1. Cache Storage: Stores commands and data blocks that are transferred from main memory.
2. Address Translation parts: Create a table of contents to convert main memory addresses to cache addresses.
3. Replacement parts: block substitution for a certain policy when the cache is full and modify address translation parts.

2. address mappings and Conversions

An address image is a correspondence between the address of a data in memory and the address in a buffer. Here are three ways to address images.

　　1. fully -connected mode

Address mapping rules: Any piece of main memory can be mapped to any block in the cache

(1) Main memory is divided into the same size data block as the cache.

(2) A chunk of main memory can be loaded into any block of space in the cache.

The correspondence of the fully-connected mode is shown in 2.3.2. If the cache block number is CB, the block number of main memory is MB, then the image relationship has CBXMB species.

Figure 2.3.3 shows the format of the table of contents and the rules of address transformation. The catalog table is stored in the associated (associated) memory, which consists of three parts: The block address of the data block in main memory, the block address after cache, and the valid bit (also known as the Mount bit). Because it is fully-connected, the directory table should have the same capacity as the number of cached blocks.

Example: a machine memory capacity of 1m,cache capacity of 32KB, the size of each block is 16 characters (or bytes). Outlines the main, cached address format, table of contents, and its capacity.

　　

　　

Capacity: 211=2048 (or 32k/16=2048) is the same as the number of buffer blocks.

advantages : High hit ratio, cache storage space utilization is high.

　　disadvantage : When accessing related memory, it should be compared with all content, low speed, high cost, and therefore less application.

　　

2. Direct- linking method

Address mapping rule: a block in the main memory can only be mapped to a specific chunk of the cache.

(1) Main memory is divided into the same size data block as the cache.

(2) The main memory capacity should be an integer multiple of the cache capacity, the memory space according to the capacity of the cache, the number of blocks in memory each block and the total number of buffers is equal.

(3) in main memory a block in the cache can only be stored in the same location in the cache.

The direct-linked mapping rule is shown in Figure 2.3.4. It can be seen that data blocks of the same block number in main memory may be transferred into the same address of the same block number in the cache, but only one block can be cached at the same time. Because the main and cache block numbers are the same, when the catalog is registered, only the area code of the incoming block is recorded.

Figure 2.3.5 shows the main, buffer address format, directory table format and address transformation rules. The main, cache block number, and intra-block address two fields are exactly the same. The catalog table is stored in high-speed, small-capacity memory, which includes two parts: the area code and the valid bits of the data block in main memory. The directory table has the same capacity as the number of cached blocks.

　　

Address transformation process: the main memory address of the block number B to access the directory memory, the read area code and main memory address in the area code e comparison, the comparison results are equal, the effective bit is 1, then the cache hit, you can directly use the block number and the address of the block in the buffer address to the cache to take the number; Can be replaced, if the valid bit is 0, you can directly transfer into the desired block.

　　Advantages : The address image is simple, data access, just check the area code is equal, so you can get faster access speed, simple hardware equipment.

　　cons : Frequent replacement operations, low hit ratio.

Example: In the above example, the main memory capacity is 1M, the cache capacity is 32KB, each block size is 16 characters (or bytes). Outlines the main, cached address format, table of contents, and its capacity.

Capacity: 211=2048 (or 32k/16=2048) is the same as the number of buffer blocks.

3. Group- Linked image mode

Group-linked image rules:

(1) Main memory and cache are divided into blocks by the same size.

(2) Main memory and cache are divided into groups by the same size.

(3) Main memory capacity is an integer multiple of the cache capacity, the main memory space by the size of the buffer zone, the main memory of each region of the number of groups and the number of cache groups.

(4) When the main memory data into the cache, the main memory and the cache group number should be equal, that is, a block in each district can only be stored in the same group number of cache space, but the group of blocks between the address can be arbitrarily stored, that is, from the main memory group to the cache group using direct image In the two corresponding groups, a total-phase-linked image is used.

Figure 2.3.6 shows the group-linked image relationship, the graph of the cache is divided into CG groups, each group contains GB block; Main memory is the cache of me, so there is a total of me, each zone has a CG group, each group has a GB block. Then, the main memory address format should contain 4 fields: area code, intra-group number, intra-group block number and intra-block address. The cache contains 3 fields: The group number, the block number within the group, and the intra-block address. There are two parts of the main memory address and the cache address, the group address is according to the direct image way, by the address to access, and the block address is the full-associated way, by content access. Group-linked address translation parts are also implemented using related memory, see figure 2.3.7.

Each cell in the related memory contains: The area code e in the main memory address and the block number B in the group, the corresponding field is the cache block address B. The capacity of the associated memory should be the same as the number of blocks cached. When the data access, according to the group number, in the table of contents to find the list of the blocks contained in the directory, and then the main memory of the visited data area code and the group block number, and the contents of the block within the group are compared. If the comparison is equal, and the valid bit is "1" then hit.

The corresponding cache block address B can be sent to the Block address field of the cache address register, and the group number and the intra-block address are assembled to form the cache address. If the comparison is not equal, the data block that was accessed is not yet in the cache, the group is replaced, and if the valid bit is 0, the cached block has not been exploited, or the original data is invalidated, and can be re-entered into the new block.

Advantages: The collision probability of block is comparatively low, the utilization rate of block is greatly increased, and the block failure ratio is obviously reduced.

Disadvantage: The difficulty and cost of implementation is higher than the direct image method.

The difference between the full-phase mappings between cache and main memory, direct mappings and group-linked mappings