The difference between Xilinx and Altera FPGAs! ----If you do not know, you will pay the price! --Reprint

I have been in contact with the FPGA since 2004, has been 8 years.
Developed Altera's Flex series and Cyclone3 series, and has developed Xilinx's VII and V5 series. I would like to talk about some of the differences between them,
In order to cause developers to pay attention to some details, so as not to pay the price, and then detours!
(1) Any one of Altera's pins can be connected to such a sig signal always @ (Posedge (SIG)) ... But Xilinx's FPGA cannot, only the CLK signal can allocate such a signal.
I first use the A company Flex series FPGA, when the FPGA and DSP EMIF connection, in order to interface bonding, using the following statements:
Always @ (Negedge (dsp_we)) ... But after using X Company's VII-FPGA, the above statement cannot be compiled. I have also committed a mistake is the DSP emif of the EMIF_CLK pin and the VII pin connection, there is no connection to the VII of the CLK type of pin, the result can not use the DSP emif SYN mode. Finally, the EMIF_CLK pin and the CLK pin of VII are connected to solve this problem when the board is modified.
(2) Altera's CLK pin can only be input, Xilinx's CLK pin is not used for clock input, can be used as normal IO.
Need to be very careful!!! Two companies on the pin type of the detailed definition, although many similar, but there are a lot of different Oh!!!
(3) Altera's IO feature does not have a pull-down resistor! Xilinx's IO structure also has a pull-down resistor.
I developed a project encountered such a problem: the transmitter, the power is required to output low level. In the use of a company's Cyclone3, in the configuration process of the PIN is tri-state + weak pull up, resulting in the output is always high, I tried, finally no solution, only on the pin welding 1k ohm pull-down resistor. Using the X Company's VII and V5 series, the pull_down characteristics of the pin can be easily solved.
With respect to the IO structure supported by both IO levels, this I think both certainly satisfies most of the applications and should be no problem.

Welcome Master to continue to add! Wei Zhiheng 20120608

The difference between Xilinx and Altera FPGAs! ----If you do not know, you will pay the price! --Reprint