The different bit width of flash and the wiring problem of CPU address line?

General Flash has 8, 16, 32 and other these different bits of the width, of course, the Flash is the number of data lines.

When Flash is connected to the address line of the CPU: there are different connection methods for different bit widths:

Generally: the bit width is 8 o'clock CPU ADDR0 and flash A0 connected, the other in order sequentially down connection;

The bit width is 16 o'clock CPU's ADDR1 and Flash's A0 is connected, the other in order sequentially down connects;

The bit width is 32 o'clock CPU's ADDR2 and Flash's A0 is connected, the other in order sequentially down connects;

How do you correspond to them? Reference Blog: http://blog.csdn.net/linweig/article/details/5556819

Take Flash with a bit width of 16 as an example:

So at this time the connection is: The CPU ADDR1 and flash A0 connected, the other in order sequentially down connection;

Take the CPU read operation as an example:

When the CPU wants to perform a 8-bit operation, it returns the high 8-bit or low eight bits of the 16-bit data to the CPU;
When the CPU wants to perform a 16-bit operation, it directly returns the 16 bits of data to the CPU;
When the CPU wants to perform a 32-bit operation, it initiates 2 reads, and the result is combined into a 32-bit return to the CPU.

Of course, some people will ask: how does he know that the low eight-bit or high eight-bit data back to the CPU, how to make two 16 bits of data into the 32-bit data to the CPU?

Because there is a middle layer called "Memory controller", the CPU to read and write operations, "memory controller" according to nor flash bit width and CPU read and write operations of the number of bits

To perform the above operation.

"Memory Controller" will help us do these things, for example, evidence:
1. When the software reads the 8-bit data on address 0, the hardware is:
① "Memory Controller" issued 0b000000000000000000000 address signal, NOR Flash on the A0-a19 line signal is: 0b00000000000000000000
②nor Flash provides a 16-bit data on the bus d0~d15, which is the 1th "smallest data unit" in NOR Flash
③ "Memory Controller" reads this 16-bit data
The ④ "Memory Controller" returns the low 8 bits of this 16-bit data to the CPU, which is a 8-bit data.

2. When the software reads the 8-bit data on address 1, the hardware is:
① "Memory Controller" issued 0b000000000000000000001 address signal, NOR Flash on the A0-a19 line signal is: 0b00000000000000000000
②nor Flash provides a 16-bit data on the bus d0~d15, which is the 1th "smallest data unit" in NOR Flash
③ "Memory Controller" reads this 16-bit data
The ④ "Memory Controller" returns the high 8 bits of this 16-bit data (note, the previous low 8 bits) back to the CPU, which is a 8-bit data.

3. When the software reads the 8-bit data on address 2, the hardware is:
① "Memory Controller" issued 0b000000000000000000010 address signal, NOR Flash on the A0-a19 line signal is: 0b00000000000000000001
②nor Flash provides a 16-bit data on the bus d0~d15, which is the 2nd "smallest data unit" in NOR Flash
③ "Memory Controller" reads this 16-bit data
The ④ "Memory Controller" returns the low 8 bits of this 16-bit data to the CPU, which is a 8-bit data.

For the other number of bits, it is roughly the same as above.

The different bit width of flash and the wiring problem of CPU address line?