The first chapter _ Computer Composition principle and architecture _ Knowledge point

1. 1. noun Interpretation

A) DRAM: dynamic random access memory; (computer main memory)

b) SRAM: static random access memory;

c) cache: cache;

d) DMA: Direct accessor access (does not require CPU execution program instructions to transmit data)

e) EEPROM: Electrically erasable programmable read-only memory

f) Accumulation register: Used to temporarily store the result information of the ALU operation of the arithmetic logic operation unit

g) The program counter (PC) is where the execution instructions are stored, which is used before the calculation.

h) The instruction Register (IR) holds an instruction that is currently executing.

i) address register (AR) is used to store the address of the memory unit to be accessed by the current CPU.

j) MTBF: Metrics for reliability

k) vliw:very Long instruction Word, an extra long instruction word, a very long instruction combination that connects many instructions together, increasing the speed of the operation.

L) The reliability of the software refers to the probability that a system does not fail to operate at a given time interval and under given conditions.

m) The availability of software refers to the effectiveness of the software in a specific use environment for a particular user for a particular purpose.

n) software maintainability refers to a set of software properties related to the ease with which software is maintained.

• o) software scalability refers to whether more users can be supported by running more instances or by using distributed processing.

p) Fully connected: means that any piece of main memory can be mapped to any piece of the cache

Q) Direct mapping

R) Group connected

s) strings connected

T) floating point number: The range of numbers that a float can represent is determined by the number of bits in the order, and the precision is determined by the number of bits in the mantissa.

u) CISC is a complex instruction system computer

V) RISC is a streamlined instruction system computer.

W) Three bus:

I. Data bus: Transmits the information, the CPU transmits the data in the same time the bus bandwidth

II. Control BUS: Transmit control signals and timing signals such as read/write, chip selection, interrupt response signal, etc.

Iii. address bus: Transfer address, which determines the addressing space of the system

x) Bus Classification

I. PC Bus

II. PCI Bus

III. ISA bus

Iv. EISA Bus

Y) Operator:

I. Arithmetic logic unit Alu

Ii. Cumulative Registers

Iii. Data Buffer Registers

Iv. Status Condition Register

Z) Controller:

I. Program Counter PC

II. INSTRUCTION Register IR

III. Instruction Decoder

Iv. Timing Components

AA) registers in the CPU

I. The program counter is used to store the address of the instruction. When the program is executed sequentially, the PC content automatically increments a value to point to the next instruction to be taken when each instruction is taken out. When the program is transferred, the transfer address is fed to the PC, and then the PC points to the new program address.

II. The program status register is used to record the information generated in the operation of the flag, the typical sign is a carry flag, 0 signs, signs, signs, overflow flag, odd and even signs.

III. Address registers include program counters, stack indicators, variable address registers, segment addresses registers, etc., for recording various memory addresses.

Iv. The accumulation register is a data register that temporarily stores the results of the operands and intermediate operations during the operation, and the accumulator cannot be used for long periods of time to hold a data.

BB) Cyclic redundancy check code in the encoding, the result of its encoding is composed of data bit + check bit, where the data bit in front, and the check bit after.

CC) instruction register is used to hold the currently executing instruction and is completely transparent to the user.

DD) The status register is used to store the information of the results of the calculation, such as carry flag, overflow flag, etc.

EE) General-purpose registers can be used for transmitting and staging data, and can also participate in arithmetic logic operations, and save the results of the operation.

FF) The main function of the decoder in the CPU is to decode the instruction.

GG) Data bus: The calculation method, the number of the data bus is an important indicator of the microcomputer, usually in line with the word length of the micro-processing consistent.

HH) Address bus: Calculation method

1. 2. Concept:

A) in a computer, there are unconditional transfers, program queries, interrupts, and direct memory access (DMA) in ways that enable data exchange between computers and external devices. The first three of these are the CPU to execute a certain program, to achieve computer memory and peripheral data exchange between. Only DMA mode, the CPU hand over the computer system bus control, do not participate in memory and peripheral data exchange between. The DMA mode is controlled by the DMA control hardware, which realizes the direct transfer of the data between the memory and the peripherals, and does not require the CPU to participate in the work. Because the DMA mode is the DMA controller hardware control to achieve data transmission, do not need the CPU to execute the program, so this way to transfer the fastest.

b) Cache: Cache

I. Cache caches have the following characteristics: It is located between the CPU and main memory, hardware implementation, small capacity, generally between a few KB to a few megabytes, the speed is generally 5 to 10 times times faster than main memory, made of fast semiconductor memory, the content is a copy of main memory content (so cache can not enlarge the capacity of main memory), The programmer is transparent, and the cache can store both the program and the data.

II. The cache memory is used to store partial copies of main memory (copies). The function of the control section is to determine whether the information that the CPU is accessing is in the cache memory, if it is a hit, and if not, there is no hit. Address the cache memory directly when hit. If a read operation is missed, the data is read from main memory and is written to the cache memory in accordance with the determined substitution principle: if the write operation, the data is written to main memory.

c) Single bus:

I. In a single-bus structure, information is exchanged between the CPU and main memory, between the CPU and I/O devices, between the I/O device and main memory, and between various devices through the system bus. The advantages of single bus structure are simple and convenient to control and easy to expand. However, because all the equipment parts are hung on a single bus, so that the structure can only be time-sharing, that is, the same moment can only transfer data between two devices, which makes the overall system data transmission efficiency and speed is limited, this is the main disadvantage of single bus structure.

d) Virtual memory

I. is a logical model of a very large memory, not any actual physical memory. It uses auxiliary memory such as disk to enlarge the main memory capacity, which is used by larger or more programs.
Virtual memory refers to the main memory-external memory level. It gives the user a much larger program address space than the actual main memory space in a transparent way. At this point, the logical address of the program is called the virtual address (imaginary address), the program's logical address space is called the virtual address space. The Physical Address (field site) is sent by the CPU address pin, which is the address used to access main memory. Set the CPU address bus width to M bits, then the size of the physical address space is represented by 2m.

e) Several fixed-point decimals

I. Original code, anti-code: 2^n-1

II. Complement, shift code: 2^N

f) Order of access to the storage device in the computer (fast to slow): Universal Register >Cache> HDD

g) Cache address image mode, the number of block collisions is sorted (large to small): Direct image > Group-linked image > Fully-connected image,

h) Interrupt System

I. Interrupt system is the general term of hardware and software for computer to realize interrupt function. The interrupt mechanism is usually set up in the CPU, the interrupt controller is set up in the peripheral interface, and the corresponding interrupt service program is set up on the software. When the interrupt source needs to get the CPU service, the request CPU suspends the current work to the interrupt source service, after the service completes, then lets the CPU return to the original work state to complete the interrupted work. Interrupt occurs from the interrupt source to make an interrupt request, interrupt processing process, the interruption system needs to solve a series of problems, including the conditions and timing of interrupt response, breakpoint information protection and recovery, interrupt Service Program entry, interrupt processing, etc. Interrupt response time, which is the time that is required from the point of interruption request to the start of the Interrupt service program.

i) assembly line:

I. Using asynchronous control to speed up the pipeline, it will obviously increase the probability of pipeline congestion, so it will not significantly improve overall performance.

j) CISC computer refers to the complex instruction set computer, which is a series of computers developed by 20世纪六、七十年代. The instruction system supported by this kind of computer tends to be multi-purpose and powerful. The instruction system is designed around narrowing the semantic gap with high-level languages and benefiting the optimization of the operating system. The complexity of the instruction system makes the design period become longer, the correctness is difficult to guarantee and difficult to maintain. Moreover, in the complex instruction system, only a few basic instructions are used frequently, and the utilization of complex instructions requiring a lot of hardware support is very low. So in the late 70, with the development of VLSI technology, RISC computers were produced.

k) RISC computer refers to the simplified instruction set computer, which has the following characteristics.

I. The instruction system contains only high frequency but not complex instructions.

Ii. The instruction length is fixed, the instruction format is few and the addressing method is few.

III. Only the access number instruction accesses the main memory, and the other instructions operate between the registers.

Iv. Most of the instructions are completed within a machine cycle, using pipelining techniques.

V. The number of universal registers has been increased in the CPU.

VI. Hard-joint logic control without micro-program technology.

VII. Use optimized compilation to effectively support high-level languages.

L) Flynn

I. SISD machine is a traditional serial computer, its hardware does not support any form of parallel computing, all instructions are serial execution. And within a clock cycle, the CPU can only process one data stream. So this machine is called a single instruction flow single data stream machine. The early computers were SISD machines, such as the Fengno Relievo architecture, such as IBM PC, the early giant machines and many 8-bit home machines.

Ii. Single instruction stream multi-data stream machine (SIMD)

Iii. SIMD is the use of a single instruction stream to process multiple data streams. Such machines are very effective in the fields of digital signal processing, image processing, and multimedia information processing.

IV. The MMXTM, SSE (streaming SIMD Extensions), SSE2, and SSE3 extension instruction sets implemented by Intel processors are capable of processing multiple data units in a single clock cycle. This means that the single-core computers we use now are basically SIMD machines.

V. Multi-instruction flow single data stream machine (MISD)

VI. MISD is the use of multiple instruction streams to process a single data stream. As a result of the actual situation, multi-flow processing is a more effective method, so MISD is only as a theoretical model, and is not put into practical application.

VII. Multi-instruction stream multi-stream machine (MIMD)

Viii. MIMD machines can execute multiple instruction streams at the same time, and these instruction flows operate on different streams of data, respectively. The latest multi-core computing platform belongs to the MIMD category, such as Intel and AMD's dual-core processors, etc. are MIMD.

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                         i.               structural redundancy   static   dynamic blending

1. static redundancy. Static redundancy, also known as shielded redundancy or passive redundancy, is commonly used for three-mode redundancy and multimode redundancy. Static redundancy masks errors that occur in the system by voting and comparison. For example, three-mode redundancy is the same for three functions, but the results of the modules developed by different people using different methods are voted, with most of the results as the final result of the system. That is, if there is an error in the module, this error can be "masked" by the correct result of the other module. It is called static fault tolerance because it does not require special testing of errors, and does not need to switch modules to achieve fault tolerance.
2. Dynamic Redundancy. Dynamic redundancy, also known as active redundancy, is the goal of fault-tolerant by means of fault detection, fault locating and fault recovery. The main way is the multi-module standby reserve, when the system detects a work module error, use a spare module to replace it and re-run. Each standby module works as the main module while it is in standby, and does not work. The former is called a Hot backup system (dual system), which is called a Cold backup system (duplex system, dual system). In the hot backup system, two sets of systems simultaneously, synchronously run, when the online subsystem detects the error, exits the service to carry on the maintenance, but is replaced by the hot backup subsystem, the standby module in the standby process its failure rate is 0; the subsystem in the cold backup usually shuts down or runs an operation unrelated to the online system. When the online subsystem fails, manual or automatic switching makes the cold backup system an online system. When running a cold backup, it is not guaranteed to work precisely from the system breakpoint, because the backup machine cannot get all the data currently running on the original machine.
3. Mixed redundancy. The hybrid redundancy technique combines static redundancy with dynamic redundancy and takes advantage of both. It first uses the fault-masking technique in static redundancy to protect the system from certain failures that can be shielded. For those that cannot be shielded, the fault detection, fault locating and fault recovery techniques in active redundancy are adopted, and the system can be reconfigured. Therefore, the effect of hybrid redundancy is much better than static redundancy and dynamic redundancy. However, because the hybrid redundancy has both static and redundant shielding function, and dynamic redundancy of various detection and positioning functions, its additional hardware overhead is quite large, so the cost of hybrid redundancy is very high, only in the case of high reliability requirements of the occasion.

II. Information redundancy
Information redundancy is the information needed to achieve normal functions, and then add some information to ensure the correctness of the results of the operation of the method. For example, the error-checking code and the correction code are examples of information redundancy. This redundant information is added in accordance with a set of predetermined rules. Words with redundant information that conform to the added rules are called code words, while those with redundant information that do not conform to the added rules are called non-code words. When the system fails, the code word may be changed to non-code word, so in the decoding process will cause non-code word fault detection, this is the basic idea of error-checking code. Error correcting code can not only detect errors, but also can be caused by the failure of non-code word corrected into the correct code word.
Therefore, the main task of information redundancy is to study a set of ideal coding and decoding technology to improve the efficiency of information redundancy. The most widely used coding technology is parity check code, hamming check code and cyclic redundancy check code.

Iii. Time Redundancy
Time redundancy is the cost of reducing hardware redundancy and information redundancy at the expense of time (that is, reducing system speed) to achieve increased reliability. In some practical applications, time redundancy can be used when the cost, volume, power, weight, and other costs of hardware redundancy and information redundancy may be too high and time is not an important factor. The basic concept of time redundancy is to repeat the same calculation multiple times, or repeat (re-execute) to achieve the purpose of fault detection.
There are many ways to implement time redundancy, but the basic idea is to repeat multiple executions of the same computational task, and then store the results of each run for comparison. If the result is the same each time, it is considered to be no fault, if there are different results, it indicates that a fault has been detected. However, this method often only detects transient faults and is not suitable for detecting permanent faults.

Iv. redundancy Add-on
Redundant attach refers to the resources and techniques required to implement the above redundancy techniques, including programs, instructions, data, and the space for storing and invoking them.

N) each addressing method

I. Immediate addressing: The Address field of the instruction indicates not the address of the operand, but the operand itself;

II. Direct addressing: Indicates the address of the operand in memory directly in the address field of the instruction format;

III. Register addressing: The operand address given in the instruction is not the address unit number of the memory, but the number of the General register (when the operand is not in memory, but is placed in the general register of the CPU, the Register addressing mode can be used);

Iv. the difference between register indirection and register addressing is that the operand in the instruction format is not the operand, but the address of the operand, and the operand can be found in memory by that address;

V. Relative addressing: Add the contents of the program counter PC to the form address in the instruction format to form the valid address of the operand.

• O) bus multiplexing, as the name implies is a bus to achieve a variety of functions. The common bus multiplexing method is bus time-sharing, which refers to the use of the same signal line on the bus at different times to transmit different signals, for example, address bus and data bus share a set of signal lines. The purpose of this method is to reduce the number of buses and improve the utilization of bus.

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1. 3. calculation method:

A) Calculation of reliability:

I. Reliability of Series parts = product of reliability of each part.

II. The reliability of the parallel components =1-the product of the component failure efficiency.

b) The time required for the assembly line to execute n instructions

I. Execution time of the first instruction + (instruction number-1) * Maximum execution time in each instruction segment execution time.

c) Memory is addressable in bytes. If the memory chip with storage capacity of 32kx8bit is used to form the address from a0000h to DFFFFH, then at least () chip is required.

I. dffffh–a0000h + 1 = 40000H = 4*16^4 = 2^2* (2^4) ^4=2^18b it into a few bytes,

II. 32kb=32*1024 = 2^5*2^10b=2^15b,

III. 2^18B/2^15B=2^3=8 tablets.

The first chapter _ Computer Composition principle and architecture _ Knowledge point