The BIOS entry address 0xffff0__ios

Always said after Power-on, the CS set to 0xffff,ip set to 0x0000, so that the address is 0xffff0, and this is the BIOS's entry address, then the CPU read the code of this address, and then the Balabala began to carry on.

Now you want to know if this address is 0xffff0 on the motherboard or on memory. Think if it is a unified address, it may be to read the ROM on the motherboard, but the picture on the reading, there is like in RAM, if it is in memory, that is when, by which program the ROM program to read in memory. Guess for yourself, this process is a fixed hardware implementation, the ROM is copied all the content in the memory of the highest section, then, 0XFFFF0 will necessarily refer to the memory of the address.

640KB~1MB Upper memory (the address of this region is assigned to ROM and the corresponding 384KB RAM is blocked.) The so-called Shadow memory technology, is to read the ROM content to the corresponding address of the RAM, the system later read from RAM data, rather than from the original ROM reading data, so as to improve speed. ）

1mb~ Extended Memory

Note:

Shadow RAM, also known as "Shadow Memory", is a specialized technique used to improve the efficiency of computer systems, and the physical chip used is still CMOS DRAM (dynamic random access memory, see the contents of this book) chip. Shadow Ram occupies part of the address space of the system main memory. Its address range is C0000~FFFFF, which is the 768KB~1024KB area in 1MB main memory. This area is also commonly referred to as a memory reservation, which is not directly accessible to user programs. The function of Shadow RAM is to store the contents of various ROM BIOS. That is, the contents of the ROM BIOS that are copied, and therefore it is called Rom Shadow, which, like the meaning of Shadow ram, refers to the "shadow" of the ROM BIOS. The current computer system, as soon as a power-on, BIOS information will be loaded into the shadow RAM in the designated area. Because the physical address of the shadow RAM is the same as that of the corresponding ROM, you can greatly speed up the computing time of the computer system by simply accessing the shadow RAM without having to access the ROM when you need to access the BIOS. Generally, the time to access the ROM is around 200ns, and the time to access DRAM is less than 100ns, 60ns, or even shorter.

During the operation of the computer system, it will be quite frequent to read the data in the BIOS or to invoke the program module in the BIOS, and after adopting the shadow RAM technology, the work efficiency is greatly improved.

Before 386 and 386, this address is different, but it is all in the highest address segment of the system memory. Under 386 for fffffff0h. Because the CS segment is 16 digits, EIP is 32-bit, in order to get a 32-bit address, 386 to the CS segment added a few fields, this is a hidden field, the system can be changed by Gdt,idt the segment selection of the field, at this time address translation is not a segment address Left 4-bit + offset address, Instead, it is the base field + offset address of CS.

The following is an example

the system resets when power is added to the system. At this time under the system of 386 before the Cs=f000h,ip=fff0h,bios address for the segment address left 4-bit + offset address squeeze namely f0000h + fff0h = ffff0h

Before 386 system addressable range of 1MB that is 00000h~fffffh< br>
cs=f000h,ip=fff0h at 386, this is invariant, but at this point the CSCS content is:
Selector = f000h (This is what you can see)

The hidden part is not available. Because in site mode, the BIOS address is the same as before 386,

But 386 addressable range 4GB is 00000000H~FFFFFFFFH, if this address (000ffff0h) as the BIOS address, the system memory is not contiguous, As a result, 386 uses hardware to place the A20~A31 address line 1 in a 1 way, which becomes fffffff0h and is used as the BIOS address.

The result of this 1 is that a field base=ffff0000h of the hidden part is not implemented by the Change Descriptor table because it has not yet entered the protection mode, and the descriptor is not yet established. This is the hardware implementation, and when a jump between segments, because the result of the 1 can not be saved, because the hardware design is from will be placed 0, so when the execution of the fffffff0h jmp, base=00000000h, at this time, the BIOS will use the following 1M memory.