The Nios II of the FPGA learning notes the reason and solution of the exception of CPU reset __ios

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Recently, when using Nios II as a project, found a strange phenomenon, in the Nios II eds software compiled good Code, burned to the chip, the first to be able to run normally, but when I press the reset button on the board, the system is stuck, and can not run again, unless the download program. Through the analysis system, the hardware design of the system and the construction of the Nios II CPU system in the QSYS system are all without problems. So why is there such a problem, and here I'll briefly introduce my system:

My system consists mainly of Nios II Cpu,sdram, reserved system timer, timestamp timer, System ID, EPCs controller, and Jtag_uart. As shown in the following figure (click on the picture to see the large HD image):

In the Qsys environment, I initially set the CPU reset vector to the EPCs, and then in Nios II eds set up a software engineering, compile, download operation is no problem, but did not have the FPGA configuration files and code to the EPCs, Therefore, the problem of reset is certain. Later, in order to facilitate debugging, in the Qsys system in the CPU reset vector is also modified to point to SDRAM, and then in Nios II eds software, after the BSP, the software compiled, download operation is no problem, but every time I press the card on the Reset button, the system is stuck dead, Can not run up again.

Remember last year when doing graduation design, once for in the system containing EPCs can not download the problem of the program, then download the program, each time in the progress of 64% times the following error, "Nios II ' launching New_configuration ' has Ecountered a problem. Dowenloading Elf Process failed. " I believe that this error is the most repugnant (note, this picture is I downloaded from the Internet, do the system has been a long time since the problem, want to get a picture like this can only Baidu):

On the internet to find a lot of problems, there is said to be SDRAM phase is not right, this I have indeed met before, but since I will SDRAM clock phase shift set to-90 degrees, basically did not encounter this problem. And the hardware itself is problematic, and this is not ruled out, but it's not the case in my system. In the end is the Sina blog or Baidu Space in a senior article found in the answer I forgot. Forgot to write down the blog address, just copy the content, save a Word document. Now this document has been able to be directly retrieved from Baidu Library, respect for others copyright, I will only send articles in the library address:

Http://wenku.baidu.com/link?url= Yoyixrjxwj0zunljgqdufdlv8wkf1kcxxxcekhgpaulhwlsxpwjr29gxgbxq-ahmrwot6oknsziaddyzrgayb6zrlu8xaahmhiikud3wpnc

His solution is to modify the two bootloader location-related options in BSP Editor and cancel the Allow_code_at_reset and enable_alt_load two options, as shown below (click the picture to see the Big HD):

This article describes the two items in BSP editor that are checked when creating a project in Nios II eds when a Nios II system without a EPCS controller is created. When a Nios II system with a EPCS controller is created, the two items in the BSP editor are not checked when the project is created in Nios II eds. Therefore, when the reset vector is SDRAM, these two options should be checked. For specific reasons, the author finds the original explanation in the relevant manuals provided by Altera.

When I check these two items in the system, generate the BSP again, and then compile and download, the processor can perform the reset properly.

Brother Xiaomei.

May 26, 2015 in Beijing to core technology