The SPI operation of isd1700 series and its simple application with limit 16

The operation of the SPI serial interface of isd1700 series follows the following protocol:

1. a spi processing starts at the falling edge of the/SS pin;

2. In a complete SPI instruction transmission cycle, the/SS pin must be kept low;

3. The MoSi pin of the chip exists in the rising edge of sclk, and the falling edge of sclk is output from the miso pin, and the low position is output first;

4. the SPI command operation code includes the command byte, Data byte, and address byte, which depends on the command type of 1700;

5. When the command word and address data are input to the MoSi pin, both the "Status Register" and the current address information are output from the miso pin;

6. One SPI processing starts when/SS is high;

7. After an SPI command is executed, an interrupt message is started and continues to be low until the chip receives the clr_int command or resets it.

Idle:

/SS = high; sclk = high; MoSi = low

SPI registers and settings related to listen 16l:

Spcr, SPI control register: initialized to spcr = 0x78; it indicates that SPI interruption is not enabled, SPI enabling, low first, host mode, sck idle high level, start along
(Descent edge) sampling.

Spsr, SPI Status Register: only 0-bit read/write, spi2x = 0, with spcr 0, 1-bit is 0, set sclk frequency to 4-frequency (Crystal Oscillator ).

ProgramDescription:

1. MCU low/SS pin:/SS = 0;

2. Run the set_play command in the SPDR register: SPDR = CDATA; // CDATA is command data

While (! (Spsr & (1 <spif); // waite until send over

3. Received bytes return value: While (! (Spsr & (1 <spif); // waite
Receive over

Return SPDR;

4. Repeat the process six times until the set_play command and address are sent and received;

* ** Note: If the 0-bit value of the first byte returned is 1, the above command fails to be sent and then resend the message ***

* ** Pay attention to the receipt sequence. After each byte is sent, one byte is received.

Process description: SPDR = data; // send data

While (! (Spsr & (1 <spif )));

Return SPDR; // return the received data or write it as "d_buf = SPDR;" to store the data.

5. Pull height/SS:/SS = 1;

6. Wait for the rdy/INT pin to decrease: While (rdy); // waite until rdy = 0

7. Send the clr_int command. (The specific process is similar to steps 2 and 3, with only difference in content and length)

×××××Think: When the spif bit is cleared, the above programs do not pay special attention to its resetting, so it is possible that the sending is completed, an error occurred while transferring to an infinite loop or failed to receive the message.

Void spi_init ()
{
Uchar temp;
Temp = spsr;
Temp = SPDR;
}

The preceding sub-functions can be used to clear spif bits.

The entire playback process is described as follows:

Voi_pu ();//
Isd1760 power-on command, send Pu command, function includes a TPU Delay Time (400/fclk), fclk is SPI bus frequency, time unit is second, frequency unit is Hz.
SPI clock rate: 2764.800 kHz. For example, the latency is 145 microseconds (rounded up ).

Voi_clr (); // sends the int_clr command. The clear rdy/INT bit is 1.

While (! Rdy); // wait until it is indeed 1,

Voi_play (); // sends the set-play command and address. For details, see.

Voi_clr (); // clear rdy/INT bit is 1

Voi_pd (); // sends the int_clr command. The command isd1760 powers down.

* ** Note that int_clr, Pu, and set_play commands both return values to verify the correctness of communication. For details, see "Development Manual ".