The stack setting mechanism of CPU is quite interesting.

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When setting SS, for example mov SS and ax, one of the following statements is also executed. This is to avoid stack setup errors, but it seems that there are also some errors. Why? Below it is the SP setting statement. When the programmer separates the SP setting from the SS setting, this mechanism seems useless.

Why does CPU command have only stack command but no queue command? Http://zhidao.baidu.com/question/77939730.html

Queue? You can use subscript to address the array. You only need to increment the subscript + address change operation, but stack operations are not that simple. You must not only use subscript addressing, but also consider subscript increment and subtraction, therefore, stack operations have dedicated push and pop operations. In addition, the CPU operation core has dedicated stack registers, but there is no so-called "queue register" because the command queue is managed by the Controller, data queues are stored in the cache/memory.

Research and Design of FPGA-based stack space Manager

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Abstract: A design structure is proposed to divide the stack space into task stacks and interrupt nested stacks to minimize the stack space. A stack space manager with automatic inspection is simulated on FPGA Devices using the VHDL Hardware language. The stack space manager is composed of logic modules with different functions. It mainly describes the design method of the Status control logic module and the address generation logic module.

With the rapid development in the fields of aerospace, industrial control, automotive electronics and nuclear power plant construction, the requirements for real-time embedded operating systems are getting higher and higher. At the same time, due to the continuous improvement of FPGA integration and speed, the hardware implementation of embedded operating systems has become a development trend. Stack management in a hardware real-time operating system plays a vital role in the real-time and reliability of the system. The traditional operating system kernel directly maximizes the stack space of each task, as a result, a large amount of storage space is wasted. In addition, the use of general Ram addressing cannot quickly protect the information of switched tasks.

Based on the above problems, this paper proposes a stack space structure, designs a stack space manager with the automatic test function, and implements it on the FPGA system of Xilinx integrated development environment.

1. Stack Space Structure

The stack space is a continuous storage space allocated according to the advanced post-release (LIFO) principle, which can meet the needs of protecting the processor status and task parameter data during Task Switching information and interrupt response [1], each task is assigned a separate job stack and an interrupt nested stack that responds to system interrupt tasks. As shown in figure 1, the stack space is divided into n task stacks and one interrupt nested stack.

The task stack mainly protects information about the switched tasks. It stores the following data: the first address of the task code, the task parameters, the local variables defined in the task, the parameters of the called function, and the return addresses of each function in the task. The interrupt nested stack stores the data of the interrupted task, including the context to be saved in case of interruption, the context to be saved in case of interruption nesting, and the local variables of the interrupted service program.

In a hard real-time operating system, when the nested stack is interrupted or interrupted, the stack address pointer switches from the task stack to the interrupted nested stack. After all the interrupt service programs are executed, the stack address pointer switches from the interrupt nested stack to the task stack to continue executing the interrupted task. Compared with the previous methods in which the operating system saves data of interrupted tasks to the corresponding Task Stack, this management method effectively saves the stack space overhead.

2 stack space manager Overall Structure

To save Ram overhead, a stack space manager with LIFO and self-check functions is constructed from the overall structure. The stack space manager structure includes a dual-port storage unit, Status control logic module, address generation logic module, and interrupt judgment logic. The status control logic module consists of three parts: the null/full sign generation logic, the binary operation logic, and the mark register group; the address generation logic module consists of three parts: read/write address logic, interrupt stack logic, and address register group.

As shown in figure 2, the state control logic module reads the fcount signal value used by the current task stack from the mark register group and transmits the fcount signal value to the binary operation logic. When the read/write control signal is valid, the binary operation logic is valid. Modify the fcount signal value and the modified value as the used output value, at the same time, it is written back to the fcount bit corresponding to the flag register. The modified signal value also serves as the input signal for generating logic for the null/full sign. The empty/full sign generates the full/empty sign for the logic, write the flag bit back to the full/Empty Bit Of the flag register. The structure of the Flag register freg is shown in 3. The initial value is 1000000000000000b.

The interrupt judgment logic is determined by the int value of the input signal and the intnesting value of the Mark register. If an interrupt occurs, the interrupt stack logic is valid. The interrupt stack logic generates read/write addresses. Otherwise, the read/write address logic is valid and the corresponding read/write address is generated.

When the read/write control signal is valid, the address of the current task is read from the stack address register group, and the stack address pointer is generated through the read/write address logic or the interrupt stack logic, the address of the inbound/outbound stack of the hos stack space. When the synchronous clock and the inbound control signal are valid during stack loading, the interrupt judgment logic determines whether there is interruption or interrupt nesting. If not, the write address logic generates the inbound stack address; otherwise, the write address is generated by the interrupt stack logic. Similarly, when an output stack is executed, when the synchronous clock and the output stack control signal are valid, the interrupt judgment logic determines whether there is an interrupt or interrupt nesting. If not, the read address logic generates the stack address; otherwise, the stack logic is interrupted to generate the stack address.

3. Stack space manager Design

To quickly and effectively protect the information of the switched tasks and meet the requirements of the automatic inspection function, two logic modules are designed in the stack space manager design, status control logic module and address generation logic module. The status control logic module generates inbound/outbound control signals and used signals. The address generation logic module generates valid inbound/outbound stack addresses. Based on the work process of the overall structure of the stack space manager, a simulated stack space manager is designed on the xup Virtex II pro chip designed by Xilinx to manage 8 tasks, the task stack depth is 64 and the width is 16.
Bit: the depth of the interrupted nested stack is 128, the width is 16 bit, And the size is 10 KB. In the design manager, ensure that the manager is quickly integrated so that FPGA resources are used as few as possible. The selection of storage units is the key. The system uses an 18 KB block ram resource on FPGA, use the IP core of the dual-port RAM storage module provided by ise 8.2i. If you select other methods, such as using triggers and registers to build a storage unit, the combination takes a long time and occupies a large amount of FPGA slices resources.

In actual embedded system applications, the depth and width of stack space can be calculated according to system requirements. The specific depth and width can be modified in the VHDL code.

3.1 Status control logic module design

Because the empty/full status flag of the status flag Register determines the stack space's inbound/outbound operations, it is critical to design the empty/full status flag. To ensure that the data can be correctly imported into and out of the stack, and to prevent memory overflow up or down, the push operation cannot be performed when the storage is full; in an empty state, you cannot perform pop operations. The process of generating control signals is shown in Figure 4.

In the design of the Status control logic module, the prio_int signal drives four multi-path selectors and selects the segments in the corresponding status mark register group, the values include full, empty, fcount, and intnesting. Empty/full and push/pop signals are combined logic input signals to generate effective push_en/pop_en control signals. The control signals determine whether the stack space performs inbound/outbound operations.

When the push_en/pop_en control signal is effective, the binary operation logic is driven to add/subtract 1 and the calculation result is output. The output signal value has three purposes: (1) generate a logical input signal as an empty/full sign, which generates empty/full signals; (2) return to the fcount bit corresponding to fregx; (3) as the output signal value of used, indicating the usage of the current task stack or interrupt the nested stack.

In the design of the empty and full signal logic modules, the combined logic judgment method is adopted for each bit of the input signal, so that the signal can be divided into two channels, A full signal is generated as the input signal of the gate combination logic. If each bit of the input signal is 1, the full signal is set to 1, and the other is set to 0. The other is used as the input signal of the gate non-combination logic to generate the empty signal. If each bit of the input signal is 0, empty sets 1, and other conditions set 0. In the design of the entire logic module, the combined logic design is used to shorten the working delay and increase the operating frequency of the system.

3.2 address generation logic module design

The stack address pointer SP determines that the data in the stack space unit is correctly written into and out of the stack. The stack address pointer SP is obtained to drive the read/write logic module and interrupt stack module. To ensure the validity and timeliness of the protected data and prevent uncertainty, you must perform operations on the data in the time series synchronization status, as shown in Figure 5.

When the address generation logic is designed, an initial value is assigned to the stack address register group. The simulation system manages eight tasks and has nine stack address registers, there are eight task stack address registers and one interrupt nested stack address register.

When the task priority PRIO signal and interrupt enable int_en signal drive a multi-channel selector at the same time, the stack address pointer SP selects the address of the current task stored in the pregx from the stack address register group, in the stack space manager, SP points to the address of the next storage unit in the stack space. If the inbound control signal is valid, the SP acts as the addressing address of the stack space and writes data. The SP adds 1. If the outbound control signal is valid, the SP minus 1, the changed sp value is used as the addressing address of the stack space to read data. After the operation is complete, the changed sp value is written back to the corresponding stack address register group pregx.

4. Simulation Result Analysis

The size of the current stack space manager is 10 KB and the width is 16 bit. Integrated and simulated in Ise 8.2i development software, 294 slices chips, 396 trigger chips, 274 input LUTs, 60 bounded iobs, and 1 brams are used in the design.

During simulation, the input data in decimal number is shown in Figure 6.

(1) When int is invalid, that is, there is no interruption or interruption nesting in the system. When push is effective, set the PRIO signal value to 2, and the data_in signal values to 32 768 and 57 908 respectively. During simulation, the output result is as follows: Used Signal values are 1 and 2, while ostcbstkptr signal values are 128 and 129, respectively. Similarly, when Pop is effective, set the PRIO signal value to 2. The simulation results are as follows: dout_out signal values are 32 768 and 57 908, and used signal values are 1 and 0, respectively, the ostcbstkptr signal values are 129 and 128, respectively. As a result, data is written and read in the task stack according to the priority PRIO of the task and the LIFO principle without interruption, in addition, the used and ostcbstkptr signal values of the current task are modified simultaneously for each valid operation.

(2) When the int value is valid, that is, interruption occurs in the system or interruption nesting exists. When push is effective, set the PRIO signal value to 6 and the data_in signal value to 8192. The simulation results are as follows: Used Signal values are 1, 2, 3, 4, the signal values of ostcbstkptr are 576, 577, 578, and 579 in sequence. Similarly, if the pop is effective, set PRIO to 6. The simulation result is as follows: The data_out signal value is 8192, used Signal values are output in sequence 4, 3, 2, 1, and ostcbstkptr signal values are output in sequence 579, 578, 577, and 576. As a result, when an interruption occurs in the system or there is an interruption nesting, data is written and read in the interrupt nesting stack according to the LIFO principle, in addition, the values of used and ostcbstkptr that interrupt the nested Stack are modified at the same time for each valid operation.

The above results show that the experiment verifies the correctness of the stack space manager and conforms to the system design requirements.

This article analyzes the structure of the stack space and protects the corresponding data information of the switched task, and rationally divides the stack space. The experimental data table shows the feasibility and stability of the system. The stack space manager can effectively save the time for the hard real-time operating system to allocate the stack space and reduce the ram storage space. From the hardware point of view, the design is simplified, the cost is reduced, and it has certain application value. Currently, it is only simulated on the experimental platform. The next step is to apply the IP core of the stack space manager to the hardware real-time operating system to improve the operating efficiency of the operating system.