The TLB stuff, __tlb.

These two days for some reason, have a good look at the Intel manual, a more systematic study of the knowledge related to TLB. The following are mainly from chapters 4th, 11th and 28th of the third volume of the Intel Manual.

We know, now memory addressing is basically the page table translation mechanism, that is, given a virtual address, through the 2~4 Layer page table, get a physical address. Although this process is typically done by hardware (MMU), there is a certain delay. Therefore, in order to speed up the process of page table translation, the general processor will have a caching mechanism for translation information, and there are two related mechanisms in Intel: TLB and Paging-structure cache.

The Tlb,cache relationship is shown in the following illustration:

When the processor is acquiring instructions or reading data, whenever a virtual address is encountered, it first finds the physical address of the virtual address through the address translation caching mechanism such as TLB, and if no corresponding entry is found, the memory translation hardware mechanism MMU the corresponding physical address by way of the page table. When the exact physical address is obtained, the memory data of the physical address will be found through the cache, and if there is no corresponding data in the cache, then it can be read in memory. Pcid

Before introducing the TLB and Paging-structure cache, it is necessary to mention PCID first. The full name of Pcid is Process-context Identifiers, and if there is no pcid, the software running on the processor each time switching CR3 will cause the entire processor's address translation cache information (including TLB and paging-structure Cache) was brushed off. And Pcid is the optimization of this process. It can be said that each process has its own pcid, which makes it possible to switch between processes without brushing off the corresponding address translation cache information in the processor.

The pcid of each process consists of a total of 12 bits 0:11 in CR3, only pcid if cr4.pcide = 1, otherwise the current pcid can only be 000H.

When logical processor creates entries in the TLB and Paging-structure cache, it hooks the entry with the current PCID, and it only looks for entries that match the current pcid when the translation address needs to use those entries.

Note: The number of logical processor is generally the same as that of processor, but when processor supports Hyper-threading (hyper-threading), there are generally two processor logical on each processor.

The hardware enforce the following two rules about PCID: if Ia32_efer. LMA = 0 or cr3[11:0]!= 000H, changing cr4.pcide from 0 to 1 will cause General-protection exception (#GP); if cr4.pcide = 1, the change of CR0.PG to 0 will result in General-protection exception. TLB

The full name of the tlbs is the translation lookaside buffers, which stores a map of page number (composed of the high level of the virtual address) to the page frame (composed of the high level of the virtual address). In addition, the line of page number and page offset (which consists of the status of the virtual address) is determined by page size: 32-bit Paging If it is a large page (4M), page number is determined by 31:22 bits of the virtual address; if it is a normal page (4K), The page number is determined by 31:12 bits of the virtual address. PAE paging If it is a large page (2M), page number is determined by 31:21 bits of the virtual address; if it is a normal page (4K), page number is determined by 31:12 of the virtual address. ia-32e paging If it is a large page (1G), page number is determined by 47:30 bits of the virtual address; if it is a large page (2M), page number is determined by 47:21 bits of the virtual address; if it is a normal page (4K), page Number is determined by 47:12 bits of the virtual address.

Each entry in the TLB stores the following information: the page frame corresponding to page number, and the access permissions that are obtained in the table addressing process: The logical-and of the R/W flags. The logical-and of the U/S flags. The logical-or of the XD flags (necessary only if ia32_efer. Nxe = 1). Additional attributes that are obtained during page-table addressing: The dirty flag the memory type paging-structure caches

In addition to the TLB caching of virtual addresses to physical address mappings, there is also a mechanism called Paging-structure cache, which is used to cache virtual addresses to a page table entry address, including: PML4 cache (ia-32e paging only) : The mapping of 47:39 bits of the virtual address to the pml4e physical address; Pdpte Cache (ia-32e paging only): The mapping of 47:30-bit to pdpte physical address of the cached virtual address; PDE Cache:for 32-bit, A mapping of 31:22 bits of the virtual address to the PDE physical address; for PAE paging, 31:21 bits of the cached virtual address to the PDE physical address mapping; for ia-32e paging, 47:21-bit of the cached virtual address mapping to PDE physical address; Global Pages

In addition to the address translation cache information that you can use to mark specific processes with PCID, you can also mark the corresponding address translation cache information through the mechanism of the global page.

First, this requires the CR4.PGE to be set to 1, and then the TLB entry is marked global if the G bit (that is, the 8th bit) in the PTE (or the most important page table entry on the large page) is 1. It is important to note that the global page this tag does not apply to paging-structure caches, it can only mark entries in the TLB.

Logical processor can translate a virtual address that is different from the current PCID item by a TLB entry marked as global. to translate a virtual address

* If the mapping of the virtual address to the physical address is found in the TLB, it is used directly;
* Otherwise, find in PDE cache, if match, then obtain the corresponding PTE physical address;
* Otherwise, find in Pdpte cache, if match, The physical address of the PDE is obtained;
* Otherwise, find in PML4 cache, if match, then obtain the corresponding Pdpte physical address;
* Otherwise, get PML4 physical address directly from CR3.

Other matters to be noted

In the addressing process, a TLB entry for the corresponding virtual address is filled in only if the P flag for each entry in the Level four page table (for ia32-e) is 1 and all reserved bits are 0. Paging-structure cache is similar. In addition, before caching the translation information, the