The UART interface is defined to receive data in DMA mode.

The problem is: I defined the UART interface of BF533 as the DMA mode to receive data, but the received data is always zero. I don't know if there is a problem with my configuration.

Please give me some advice. Thank you. The configuration is as follows:
Void init_dma (void)
{
* Pdma6_peripheral_map = 0x6000;
* Pdma6_config = wdsize_8 | di_en; (transmitted in bytes | interrupted upon completion of reception)
* Pdma6_x_count = 0xa; (buffer of 10 bytes)
* Pdma6_x_modify = 1;
}

Main ()
{
Unsigned char rec_buffer [10];
Init_dma ();

.......
* Pdma6_start_addr = (unsigned char *) rec_buffer; (the start address of DMA)
* Pdma6_config = (* pdma6_config | dmaen); (DMA enabling)
* Puart_ier = 0x1; (first time, request data)
While (* pdma6_irq_status & 0x8); (waiting for completion)
............
}

Send data to BF533 through the Super Terminal. No matter what characters are entered, after the DMA is completed, check the value of the array rec_buffer. All values are zero. I don't know why.

Please give me some advice! Thank you ~

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Note that ssync must be added to each MMR value assignment statement.

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After ssync is added, the debugging still fails to receive data.

I added the ssync statement to the end of each memory-mapped registers operation. The debugging still does not work. I don't know why.

One step to the while (* pdma6_irq_status & 0x8); input 10 characters to Blackfin through the serial port, you can jump out of this while loop, it is reasonable to receive the data. but read the array, but all are 0. I don't know why.

Please give me some comments ~ Thank you ~

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Example of UART communication in vdsp

In the samples of the installation directory, listen to the video tutorial of Adi.

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I searched for it and couldn't find the example program you mentioned below my installation path. there are two samples folders, but they are not from the Blackfin Processor. I also checked in. the code in is not designed to UART.

My visualdsp version is 4.0. I don't know if our version is different. Why can't I find it?

I tried to set UART to DMA transmission mode and print it through serial port. you can achieve this. however, UART is used to receive data, but it is always zero. no problem found. depressing ~~

 

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No need to add ssync () to configure DMA ();
Should your DMA be configured in autobuffer mode? Why is the interruption still used?
While (* pdma6_irq_status & 0x8); what about it?
The program seems to be a bit messy. It is recommended to build a regular framework. It doesn't matter if the DMA interrupt is added, so that you don't need to enable the DMA once, so that you can enable the DMA before the UART.

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Vdsp does not have a c-language DMA mode UART example. Let me give it to you.
/* Headerfile declarations */
# Include <cdefbf533.h>
# Include <signal. h>
# Include <stdio. h>
# Include <sys/exception. h>
# Include <sys/excause. h>

/* Input CLK frequency */
# Define clkin 27000000 // 27 MHz

/* UART baud rate selection */
# Define baud_rate 115200 // 115.2 kbps
// # Define baud_rate 921600 // 921.6 kbps

Typedef signed Char int8_t;
Typedef short int16_t;
Typedef long int32_t;
Typedef unsigned char uint8_t;
Typedef unsigned short uint16_t;
Typedef unsigned long uint32_t;

# Define txlen 256

# Define rxlen 2560

# Define ssync () ASM ("ssync ;")

Ex_interrupt_handler (uart_dma_isr_tx );

Ex_interrupt_handler (uart_dma_isr_rx );

Void init_interrupts ();
Void init_dma_tx ();
Void init_dma_rx ();
Void init_uart ();

/* Buffers */
Unsigned char autobuffertx [txlen] = {
# Include "data. dat"
};
Unsigned char autobufferrx [rxlen];

Void main ()
{

Init_interrupts ();
Init_dma_tx ();
Init_dma_rx ();
Init_uart ();

While (1)
{
ASM ("NOP ;");
}

}
Void init_interrupts ()
{
* Psic_iar1 = 0x34666666; // dma6 (uartrx ),
// Dma7 (uarttx)
Ssync ();

Register_handler (ik_ivg10, uart_dma_isr_tx );

Register_handler (ik_ivg11, uart_dma_isr_rx );

* Psic_imask = 0x0000c000; // dma6 (uartrx) & dma7 (uarttx)

Ssync ();
}

/* Transmit ISR */
Ex_interrupt_handler (uart_dma_isr_tx)
{
/* Clear transmit interrupt */
* Pdma7_irq_status = 0x3;
Ssync ();
}

/* Receive ISR */
Ex_interrupt_handler (uart_dma_isr_rx)
{
/* Clear receive interrupt */
* Pdma6_irq_status = 0x3;
Ssync ();
}

/* Uart tx init */
Void init_dma_tx ()
{
Int ttemp;

* Pdma7_config = 0x1080;/* ENA autobuff, linear block, 8bit, source */

Ssync ();

* Pdma7_peripheral_map = 0x7000;/* UART-TX */

Ssync ();

* Pdma7_x_count = txlen;
Ssync ();

* Pdma7_x_modify = 1;/* linear */
Ssync ();

* Pdma7_y_count = 0;
Ssync ();

* Pdma7_y_modify = 0;
Ssync ();

/* Enable sport0_dma_start_hi_addr */

* Pdma7_start_addr = autobuffertx;
Ssync ();

Ttemp = * pdma7_config;
* Pdma7_config = (ttemp | 0x01);/* enable DMA */
// * Pdma7_config = 0x1081;
Ssync ();
}

/* Uart rx init */
Void init_dma_rx ()
{
Int ttemp;

* Pdma6_config = 0x1082;/* ENA autobuff, linear block, 8bit, destination */

// * Pdma6_config = 0x1052; Testing

Ssync ();

* Pdma6_peripheral_map = 0x6000;/* UART-RX */

Ssync ();

* Pdma6_x_count = rxlen; // Len;
Ssync ();

* Pdma6_x_modify = 1;/* linear */
Ssync ();

* Pdma6_y_count = 0;
Ssync ();

* Pdma6_y_modify = 0;
Ssync ();

/* Enable sport0_dma_start_hi_addr */

* Pdma6_start_addr = autobufferrx;
Ssync ();

Ttemp = * pdma6_config;
* Pdma6_config = (ttemp | 0x01);/* enable DMA */
// * Pdma7_config = 0x1083;
Ssync ();
}

 

/* UART driver initialization */
Void init_uart ()
{
Uint32_t divisor; // uses to hold the calculated divisor Value
Uint8_t msel; // multiplier msel [] of pll_ctl register []
Uint8_t SSEL; // divisor SSEL [3:0] of pll_div register [3:0]

/* Line control setup: 8-bit data, no parity, 1 stop bit */

* Puart_lcr = 0x0083;

/* Read the msel from pll_ctl register */

Msel = (* ppll_ctl)> 9; // read msel [5:0] From pll_ctl

Msel & = 0x3f; // clear all bits unique T msel []

/* Read SSEL from pll_div register */

SSEL = * ppll_div;
SSEL & = 0x0f; // clear all bits unique t ssel []

/* Divisor calculation:
* Sclk = (msel * clkin)/SSEL if df = 0
* Sclk = (msel * clkin/2)/SSEL if df = 1
* Divisor = sclk/(16 * baud_rate)
*/
Divisor = (msel * clkin)/(SSEL * 16 * baud_rate ));

If (* ppll_ctl & 0x1) // If df = 1, clkin/2 is going to PLL

{
Divisor/= 2; // divide by 2
}

/* Baud rate setup: 115.2 kbps */
* Puart_lcr | = dlab; // enable divisor latch access
* Puart_dll = divisor;
Ssync ();
* Puart_dlh = (divisor> 8 );
Ssync ();
* Puart_lcr & = ~ Dlab; // disable divisor latch access
Ssync ();

* Puart_ier = 0x3; // enable interrupts for receive & transmit

// * Puart_ier = 0x2; // enable interrupts for transmit

// * Puart_ier = 0x1; // enable interrupts for receive

Ssync ();
* Puart_gctl = ucen;/* UART clock enable */
Ssync ();

}

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Thank you for your guidance. After debugging the oppop code and believing that the hardware is correct, we compared the oppop code. previously, I reversed the DMA direction. dizzy ..... thank you for your help.