The frequently asked questions and start-up introduction of Godson Pmon

First, common commands

Memory test

Mt-v

Newmt

Download kernel

Download load tftp://10.2.5.22/vmlinux.32 over the network

Download Load/dev/fs/[email protected]/boot/vmlinux.32 via hard drive

Download load//fs/[email protected]/boot/vmlinux.32 via SD card

Upgrade BIOS load-r-F 0xbfc00000 tftp://10.2..5.22/gzrom.bin

Output to serial port from hard disk boot core g console=ttys0,115200 init=/bin/sh root=/dev/hda1 RW

Display output to video card boot core from hard disk G Console=tty root=/dev/hda1 FB =vfb:1

Second, frequently asked questions

1. The serial port does not have the word

Can be checked in the following order

A. Whether the BIOS that is burned into the flash chip matches the motherboard

B. Whether there is a crystal oscillator whether the Lil bit position can be the frequency of the time-doubling relationship is appropriate

C. Whether the serial port is connected to the serial line whether it is a cross-line host serial port is available to set the device baud rate is

No yes)

D.CPU can be taken from LPC Flash

2. How to do the serial garbled

Whether the baud rate of the serial port in the A.bios is consistent with the baud rate setting on the serial terminal

The serial line is intact (can be replaced by a serial line to try

When the serial port is initialized in the BIOS, the multiplier factor is set to the same as the external clock frequency:

LEAF (Initserial_uart)

Li A0, gs3_uart_base

Li t1,128

# Addiu a2,a0,3

SB t1,3 (A0)

Li t1,0x12 # divider, highest possible baud rate, 33M

# li t1,0x0e # divider, highest possible baud rate, 25M

SB t1,0 (A0)

Li t1,0x0 # divider, highest possible baud rate

SB t1,1 (A0)

Li t1,3

SB t1,3 (A0)

........................................................

The formula is calculated as follows 115200hz X 0x0e = 25m/16

115200hz X 0x12 = 33m/16

The corresponding kernel in the serial frequency also needs to be changed to the main modified files have

Include/asm-mips/serial.h

Include/asm/serial.h This file is linked to Include/asm-mips/serial.h

Arch/mips/kernel/8250-platform.c

How to choose LPC Serial in BIOS

In the BIOS configuration file inside the conf.3aconf, with the Use_lpc_uar option selected will use the LPC serial port

1.

#

#option Use_lpc_uart

#

What if I want to use the UART_0 serial port?

Disable Use_lpc_uart in the configuration file and choose between UART0 and UART1

Modify the gs3--uart--in the corresponding B/.

Definition of Base

#define Gs3_uart0_base 0XBFE001E0

#define Gs3_uart1_base 0xbfe001e8

#define Gs3_uart_base Gs3_uart0_base

If the serial port is never out of the word available ejtag see if the CPU has run up.

3. What to do if you run into memory

In the time often ran into memory run fly problem read. Source code can see that this problem occurs

The code and data extracted from it are copied into the memory. As long as it is inside

It is correct to initialize and the current set frequency range is appropriate and this problem does not occur. So I met this

A problem requires checking memory

Whether the memory is placed in the memory slot

Whether the crystal oscillator of the memory has the crystal frequency, the multiplier coefficient is suitable

Are the memory strips and the crystal oscillator good?

There is no problem with the slots in the memory strips (for example, some MCP68 boards can only use MC1

4. If the memory is not automatically detected and configured manually on the board, the option channel size is set on the card and the board

The location and size of the storage (two controllers can lead out four slots each controller corresponds to two slots)

5. Correct DDR information is read through I²C on the board that automatically detects and configures the memory

Whether the memory parameters match

4. What to do if the NIC is not available

1.pmon whether the device can be found DEVLS:RTE0,FXP0,RTK0,RTE0,EM0

2. NIC is not damaged

3. is the support for the NIC added to the Conf configuration option for the corresponding Bonito?

4. When the network card ping is lost packet 3a3 inside RTL8169 network card driver inside whether to change something?)

Whether the PCI base address is set correctly

Under the corresponding Bonito check PCI/PCI_MACHDEP.C: PCI device with CPU needs to change this)

169/*set PCI BASE0 Address and window size*/

Pci_local_mem_pci_base = 0x80000000;

171 #ifdef LS3_HT

172 #else

173 BONITO_PCIBASE0 = 0x80000000;

174 #endif

5. What to do if the hard drive cannot be found

1. Are the data and power cords of the hard drive connected?

2. Does the configuration file in the BIOS support the hard drive

3. If the Accept Port window with the HT port to bridge HT is open

#if 1//open RX SPACE in HOST

ttydbg ("HT RX DMA address enable\r\n")

DLI T2, 0x90000efdfb000060

Li T0, 0xc0000000

SW t0, 0x0 (T2)

Li T0, 0x0080fff0

SW t0, 0x4 (T2)

ttydbg ("HT RX DMA address ENABLE done 1\r\n")

Li T0, 0xc0000000

SW t0, 0x8 (T2)

Li T0, 0x00008000

SW t0, 0xc (T2)

ttydbg ("HT RX DMA address ENABLE done 2\r\n")

Third, BIOS boot

The BIOS is the earliest initialization and boot firmware when the system starts. Primary completion initializes the processor state, initializes the cache

and DDR, partition and map address space, device self-test, boot kernel functions.

1. Processor State Initialization

This process primarily initializes some registers of the CP0 to set the CPU exception handler entry. System reset or up

Power is performed first.

/* note!! Not more this instructions here!!! Right now it ' s full! */

Mtc0 Zero, Cop_0_status_reg

Mtc0 Zero, Cop_0_cause_reg

Li T0, sr_boot_exc_vec/* Exception to Boostrap location */

Mtc0 T0, Cop_0_status_reg

La SP, stack

La GP, _GP

Sr_boot_exc_vec = 0x04000000, tells the CPU to use the exception entry for ROMKSEG1 space in

Bev is typically set to 0 after the operating system starts. Additionally set the GP,SP register since the DDR is initialized later from

The load data in flash needs to be used.

Disassembly of section. Text:

80010000 <_ftext>:

80010000:00 (e-mail protected]@@.. ' [E]. ' <. ' [Email protected]

80010010:01 1d 3c C0 BD, 1c 3c E0 C0 9c ... <...g...<...g

80010020:00 XX E0 BF 3c 1c in a few 8c ........ < B4. C.

80010030:0f (0f) 0d 00 03 24.. C4. C8. c....$

80010040:00 (AC), FF FF, FE FF 60 14. c....$. C $.. `.

80010050:00 xx F8 02 11 04 00 00 00 00 ......

The following link scripts are implemented

ENTRY (_start)

SECTIONS

{

. = 0xffffffff80010000;

. Text:

{

_ftext =. ;

* (. Text)

* (. Rodata)

* (. rodata1)

* (. Reginfo)

* (. Init)

* (. Stub)

* (. gnu.warning)

} =0

_etext =.;

。。。。。。。。

_GP = ALIGN (+) + 0x7ff0;

GP is initialized to reduce the number of times a global variable is addressed. And the value of the SP is

MIPS64EL-LINUX-NM Gzrom | grep stack

ffffffff80ffc000 T Stack

Exactly corresponds to start. S in the

_start:

Start

. GLOBL Stack

stack = start-0x4000/* Place Pmon stack below Pmon start in RAM */

and start. The _start in S is from the compiled link script Zloader/ld.conf.s

Kentry (_start)

8 SECTIONS

9 {

10

11. = 0xffffffff81000000;

......................

The code placed below is the address of some agreed interrupt vectors see "MIPS processor design perspective" 85

Page. They do not immediately execute the startup code and will actually proceed

Locate

La S0,start

Subu S0,ra,s0

and s0,0xffff0000

Li T0,sr_boot_exc_vec

MTC0 T0,cop_0_status_reg

MTC0 Zero,cop_0_cause_reg

. Set Noreorder

This code is mainly to get the value of S0. In this code, the RA is still based on the 0xbfc0000 to the BIOS flash.

The address of the S0 is based on the compiler-specified start0x81000 address disassembly code as follows

81000c38 <locate>:

Locate ():

81000c38:3c108100 lui s0,0x8100

81000c3c:66100000 Daddiu s0,s0,0

81000c40:03f08023 Subu S0,ra,s0

81000c44:3c01ffff lui at,0xffff

81000c48:02018024 and S0,s0,at

81000c4c:3c080040 lui t0,0x40

81000c50:40886000 mtc0 T0,C0_SR

81000c54:40806800 mtc0 Zero,c0_cause

81000c58:3c14bfe0 lui s4,0xbfe0

So s0 = 0xbfc00000-0x81000000, which is used to fix the specified address in the step of compiling the link and access the Flash core

The offset of the real address of the slice. Also s0 if 0 how to indicate that the system is booting from RAM. This point in reading

Start. s in the code need to be careful not to forget. Like start. s function for serial printing

LEAF (stringserial)

Move A2, RA

#ifdef rom_exception

Li a1,0x3ec00000

Addu A1, A0, A1

#else

Addu A1, A0, S0

#endif

Lbu A0, 0 (A1)

..............................................

The next very important operation is to open the address space on the system with the size of a bit. This is the CPU with 2F and before

There is a difference in the BIOS because the LS3A and later chips are 64-bit supported and the subsequent code will

A 64bit address such as a memory self-test enables the SMB bus to appear.

Open 64-bit Address Space

Mfc0 T0, Cp0_status

Li T1, 0x00e0 # {cu3,cu2,cu1,cu0}<={0110, status_fr<=1

Or t0, t0, T1

Mtc0 T0, Cp0_status

. Set MIPS64

Enable the user segment, supirvisor segment, kernel segment of the zero bit access simultaneously set the system to

Kernel model. For ease of commissioning some boards with 7-segment digital tube below this code is to the digital tube

The 0x99 is written inside. This makes it easy for the debugger to determine where the program has probably been executed.

Li a0,0x900000001ff00080

Li T0,0x99

SB t0,0x0 (A0)

After doing this, the main processor core starts initializing the secondary cross bar and DDR and enters from the processor core.

Wait. Multi-core boot sequence can refer to "Godson 3A launch Summary".

Initialization of the 2.ddr/tlb/cache

Godson 3 A and later multicore chips each processor has not less than 4 processor cores each core has its own

The command cache, data cache, command TLB, data tlb. These are initialized by each of the cores themselves. The nuclear inter-

Level cross bar connected to level two cache two cache can be initialized via the main processor core. Also connected at level two

The dual-channel memory controllers (MC0 and MC1) on the cross bar are also typically initialized by the main processor core.

The main processor core will first jump to Core0_start to execute

#ifdef LS3_HT

b Core0_start

Nop

#endif

Start with the code below to determine if it is starting from RAM if it means that the DDR has initialized the completion instruction has been

It is executed in memory so you can jump directly to Initmips to execute.

Bnez s0,1f

Nop

Li a0,128

La V0,initmips

JR V0

Nop

1:

Otherwise, the memory and cache must be initialized first. You'll see later.

#include "loongson3_fixup. S

This is to prevent some speculation of illegal access to the execution of the crash.

Then call #include "loongson3_ddr2_config. S "To perform memory initialization and set level two cross

Bar's window. The two level cross bar is necessary to route the low 256M of system memory into the memory

The DDR controller. If you want to use a PCI device such as a network card, you must also route the PCI DMA space to a

into the memory strip of the DDR controller.

After the initialization of the memory, it is theoretically possible to use it. But can only be accessed through the Uncache way because then

The cache has not been initialized yet. However, the Uncach method is slower to visit, so you need to initialize the cache first. As for

TLB Although Pmon is not used inside, but in order to avoid guessing the execution may result in an unexpected hit of the TLB

The Entry_hi of each entry for the TLB needs to be initialized to the unmapped address to ensure that the BIOS is not running during the

A TLB hit may occur.

Here is the code that initializes the TLB

LEAF (Cpu_tlbclear)

Li A3, 0 # First TLB index.

Li A2, pg_size_4k

MTC0 A2, Cop_0_tlb_pg_mask # Whatever ...

1:

MTC0 Zero, Cop_0_tlb_hi # Clear entry high.

MTC0 Zero, Cop_0_tlb_lo0 # Clear entry low0.

MTC0 Zero, Cop_0_tlb_lo1 # Clear entry Low1.

MTC0 A3, Cop_0_tlb_index # Set the INDEX.

Addiu A3, 1

Li A2, 64

Nop

Nop

TLBWI # Write The TLB

BNE A3, A2, 1b

Nop

JR RA

Nop

END (Cpu_tlbclear)

Clearing each of the TLB's keys clears 0, so you can avoid hitting some indeterminate state after the CPU restarts. Pick up

To initialize the TLB from the wired register to the last TLB entry specified

LEAF (Tlb_init)

MTC0, cp0_wired

MTC0, Cp0_pagemask

Tlb_flush_all:

Lui A0, 0x8000

Addiu A1, $64

#a0 =kseg0,a1 = tlbsize, V0, v1, A3 used as local registers

MTC0, Cp0_entrylo0

MTC0, Cp0_entrylo1

MFC0 V0, cp0_wired

Addu v1, $ A, A0

1:SLTU A3, V0, A1

BEQ A3, $1f

Nop

MTC0 v1, Cp0_entryhi

MTC0 V0, Cp0_index

Tlbwi

Addiu v1, v1, 0x2000

BEQ, $1b

Addiu V0, V0, 1

1:

# # #tlb_init finish####

Tlbp

JR RA

Nop

END (Tlb_init)

###############################

Note that this time the value of 0x80000000 + 0x2000 * N is written to Entry_hi because the address is

Unmap so that it can be guaranteed to not hit every time and then all the first side of the mapped space

The TLB Miss will appear in the memory visit. Then jump to the code that initializes the first-level cache

LEAF (Godson2_cache_init)

# # # #part 2####

Cache_detect_4way:

mfc0 T4, Cp0_config

Andi T5, T4, 0x0e00//Get size of L1 cache

SRL T5, T5, 9//T5 = L1 Cache Size IC

Andi T6, T4, 0x01c0//T6 DC size

Srl T6, T6, 6

Addiu T6, T6, #4way

Addiu T5, T5, #4way

Addiu T4, $1

Sllv T6, T4, T6//

SLLV T5, T4, T5

Addiu T7, $4//Calculate the Icache/dache size and size of each group 16k

# # # #part 3####

Lui a0, 0x8000//start address of KSEG0 CACHED

#addu A1, T5,

#addu A2, T6,

Li A1, (1<<14) #64k/4way

Li A2, (1<<14)

Cache_init_d4way:

#a0 =0x80000000, A1=icache_size, a2=dcache_size

#a3, V0 and v1 used as local registers

MTC0, Cp0_taghi

Li T0, 0x22

Mtc0 T0, CP0_ECC

Addu V0, $ A, A0

Addu V1, A0, A2

1:SLT A3, V0, V1

BEQ A3, $1f

Nop

MTC0, Cp0_taglo//

To the current cache line

Cache Index_store_tag_d, 0x0 (v0)//Initialize the first path corresponding to the Tag field of the cache line

Cache Index_store_tag_d, 0x1 (v0)//Initialize the second path corresponding to the Tag field of the cache line

Cache Index_store_tag_d, 0x2 (V0)

Cache Index_store_tag_d, 0x3 (V0)

BEQ, $1b

Addiu V0, V0, 0x20

1:

Same as for ICAHCE. The process of initializing is as follows

Cache_flush_i4way:

Addu V0, $ A, A0

Addu V1, A0, A1

MTC0, Cp0_taglo

MTC0, Cp0_taghi

MTC0, CP0_ECC

1:SLT A3, V0, V1

BEQ A3, $1f

Nop

Cache 0x08, 0x0 (v0)/*index_store_tag_i*/

Cache 0x08, 0x1 (v0)/*index_store_tag_i*/

Cache 0x08, 0x2 (v0)/*index_store_tag_i*/

Cache 0x08, 0x3 (v0)/*index_store_tag_i*/

BEQ, $1b

Addiu V0, V0, 0x20

1:

Cache_init_finish:

ttydbg ("\r\ncache init ok\r\n")

JR RA

Nop

Cache_init_panic:

ttydbg ("\r\ncache init panic\r\n")

1:B 1b

Nop

. End Godson2_cache_init

Similarly after the initialization of the Scache is similar to the corresponding Tat_lo, Tag_hi clear 0. So all first-time visits

Cache MIPSS will be accessed directly to the mem, and the physical address of the memory

Bit to set the tag field as to which item the tag is replaced is implemented according to the immediate substitution algorithm.

In this way, you can use the cache to access the 0xbfc0000 corresponding instructions and data for this to first put the current

The address of the RA (0xbfc00000) is implemented on the 0XDFFF, so that the PC becomes the address where the 0X9FC begins.

#if 1

Printstr ("Jump to 9fc\r\n")

Lui t0, 0xdfff ####################### go to 9FC

Ori t0, t0, 0xFFFF

Bal 1f

Nop

1:

And Ra, RA, t0

Addiu Ra, RA, 16

JR RA

Nop

#endif

In addition, you need to configure the cache behavior for KSEG0 segment access to cache mode. Otherwise, even if the PC address is

Cached's actual visit to the bank is still uncache.

#if 1

Mfc0 $4, $16

and $4,0XFFFFFFF8

The K0 domain of the $4,0x3//config register is 0x3

MTC0 $4,$16

TTYDBG ("cache Enable done\r\n")

Nop

#endif

The first level cross BAR operation is then performed. (primarily for compatibility with previous Pmon and PCI

Device, which implements a mapping of 64-bit addresses to 32 addresses so that the CPU can access the HT space with a 32-bit address/PCI null

Room). Finally, the BIOS executable code and the data inside the flash are copied to the compilation script Ld.script specified accordingly

Party. Once all of the above actions are complete, you can jump to initmips to execute them completely.

This article is from the "Store Chef" blog, so be sure to keep this source http://xiamachao.blog.51cto.com/10580956/1681708

The frequently asked questions and start-up introduction of Godson Pmon