The hardware solution of Rs compiling code in broadband wireless access network

First, the introduction
Error control technology plays an important role in improving the reliability of communication system. RS code has a strong ability of correcting errors, which can correct random errors and rectify sudden errors, and is widely used in communication systems. RS encoding scheme is relatively simple, not to repeat in this, only in the final test process to give the test results. But the decoding complexity of RS code is high, the mathematical operation is big, the hardware and software decoding scheme in our country can not meet the transmission demand of high speed, it is generally applicable to below ten MHz. In this paper, based on the Euclidean algorithm (Euclidean algorithm) and IDFT RS decoding scheme, the FPGA chip is used to realize the stream decoding scheme with the symbol rate of 32.5 MHz on the GF (28), the maximum delay is 640 NS, and the parameters can be flexibly set according to the need. 
Two, the structure of RS code
For code length n=q-1, the RS code generating polynomial g (x) = (X,ΑI∈GF (q) has the minimum code distance δ=2t+1, can correct t a random or burst error.

Error, when the symbol rate is 10-3 MHz, the error rate can be improved to less than 10-7 in the case of a channel error bit. 
RS code decoding scheme with IDFT combined with tri-Euclidean algorithm
RS code is a subclass of BCH code. RS decoding algorithm is generally divided into 3 steps: Adjoint calculation, the acquisition of key equations and the solution of wrong pattern. How to calculate error location polynomial by adjoint is the most difficult and critical step in RS decoding.
There are many methods to solve the connection polynomial, but the Euclidean algorithm has few data storage and simple control, which is also proved to be suitable for hardware realization through VC simulation, so it has been recommended by the United States Ccsds agency. The Euclidean algorithm is used to get the join polynomial, the time and the number of errors are proportional, but the probability of multiple errors is much lower than the error, so from time to consider, the use of Euclidean algorithm is a better choice.
After obtaining the key equation, the method of frequency domain is used to solve the error value with the combination of the shortest linear shifter and the Idft transform, and the logic unit is simple and time-consuming. Although more resources are needed in IDFT, for GF (2n), when n<10, the transform domain decoder is much simpler than the time domain decoder [2].
So the method of Euclidean algorithm and frequency domain processing is adopted in the project, and the result is good. The Euclidean algorithm [3] steps as follows:

(2) Iteration according to the listed method

Implementation of RS decoding on FPGA
The design of the finite-field multiplier and control logic is most important in the above 3 steps: The operation speed of the finite field is the bottleneck restricting the speed of decoding, and the control logic determines the decoding process. The Software development tool of hardware circuit provides a simple way to design complex circuit. This system adopts the method of combining Quartus with the third party software, and designs most function modules with VHDL language. Especially in the multiplier design, multiplier, variable multiplier and multiplier, finite field multiplier with variable multiplier, after logic synthesis and optimization design, the operation speed can be completed in the 6.8 NS and 11.6 ns respectively, which can meet the requirement of system symbol rate. 
The solution of 1 adjoint type s0,s1,...,s2t-1
Order R1,r2,...,rn to receive RS code words, taking into account the RS system code monitoring matrix properties are:

This allows the multiplication circuit to be constructed, as shown in Figure 1. 



By using this simple logic circuit, the adjoint formula can be realized and the adjoint type can be obtained when the receiving code word is at the end of input (less than 3 NS). When the s0,s1,...,s2t-1 are 0 o'clock, the decoding is finished, and the sign is given. Otherwise, start step 2;
2. The calculation of error location polynomial by adjoint method
On the basis of obtaining the adjoint type, the error-locating polynomial can be solved:

The solution process is shown in Figure 2. 



As can be seen from Figure 2, when the adjoint formula is completed, the clock rises along the feed into the control Unit 2 to initialize the divisor polynomial register, while control unit 1 initializes the divisor polynomial register to x2t. The control Unit 1 controls the data change of the divisor polynomial register under the driving of the clock. The Control Unit 2 controls the divisor polynomial registers to carry on the substitution of the data in the clock driving. The quotient polynomial of the output is used to derive the key equation of iteration. When the output is less than t=8, the calculation ends, start step 3, at the same time, the whole system to clear zero, ready for the beginning of the next process.
This design requires only 2 sets of registers and a group of division units, with less resource consumption. The parallel algorithm and the trapezoidal topological structure used in the Block diagram guarantee the speed of the Euclidean algorithm. When t≤8, each additional error position, time consuming will increase the NS. However, because the probability of a few errors is far greater than the probability of multiple errors, the nature of the time-consuming and error is exactly what we expect. (☆ Introduction to Programming Network ☆)
It should be pointed out that the further improvement of system speed is limited by the calculation speed of inversion, the inverse has no definite mathematical structure, and the method of look-up table is usually used, which is the bottleneck of increasing the speed of restriction. But for streaming decoding, the above structure can satisfy the requirement. 
3. Using the shortest linear shifter synthesis and idft transform to get the wrong pattern
The hardware implementation diagram is shown in Figure 3. Using St-1,st-2,...,s1,s0 and σ (x) to generate s0,...,st,st+1,...,sn-2,sn-1, that is, the s sequence by cyclic iteration, the resulting St is compared with the st produced by the first-stage adjoint circuit, which represents the σ (x) obtained by the Euclidean algorithm. is correct, at this time the flag output flag bit "0", unequal to indicate decoding error, output flag bit "1". The parallel error pattern EN-1,EN-2,...,E0 can be obtained by the IDFT operation of S sequence, and the correct code word can be obtained by reading the received code word from the cache and the error pattern.
It takes only 255 clock cycles to complete the entire calculation, much faster than the time domain decoding algorithm. In time domain operations, only the money (chien) search [1] (A practical method of Qian Tian in 1964 for the root of σ (x)) requires 255 operations, in each operation, we also have to do 8 times polynomial calculation, when the error location, then the error value of the solution, the cost of time can be seen. However, using the scheme provided in this paper, the IDFT transformation and S-sequence of the solution needs to be synchronized, the use of more hardware resources, but the cost of resources in exchange for the speed of improvement.