The latest application of Protel99se signal integrity

 

1. Set the ing type of the passive device R, C, and L under the menu preferences.
2. Set the LAYER thickness and copper thickness in layer stack mananger.
3. Set the si rules in DESIGN/design rules/signal integrity.
4. Run TOOLS/signal integrity, run the import IBIS-FILE on the signal integrity interface, and
Import the IBIS model file of the analysis chip.
5. Use a text editor to edit Design Explorer 99.
Selibrarysignalintegrityuseru_parts.hdr, which specifies all available PROTEL99SE
The device model, ASCII format, is easy to understand. Here you can create a new device model and
Pin specifies the pin macro model imported in step 1. You can specify each pin and change the device name to the device attribute in the PCB.
(Of course you can change the COMMENT) to save the disk.
The following is a simple device format:
TI! SN74221N PQ [16] TYP ["DIC"]
IN [1--3, 9--11] ("TTL_000_S0_in.mac "),
[6, 7, 14, 15]
OUT [4, 5, 12, 13] ("TTL_000_S0_out.mac ")
BI [6, 7, 14, 15]
VCC [16]
GND [8]
6. Return to the PCB interface of protel99se and run Reports/signal integrity. If ICs
The valid models column identifies the model of the relevant device model you edited earlier. It indicates that the configuration is successful. You can
Returns the detailed signal integrity rules set in DESIGN/design rules/signal integrity, and uses
Tools/design rules check. Similarly, the signal integrity after running TOOLS/SIGNAL INTEGRITY
You do not need to set the pin model of the signal one by one on the interface. It has automatically identified the signal according to the settings in the u_parts.hdr file.
You can directly select a signal for analysis.
Advantage: the buffer model can be specific to the pin, and the batch signal analysis result is much more accurate than the default model.
Accurate batch analysis of overhead and underhead in Reflection Analysis, and more accurate single crosstalk can be compared in the signal integrity interface.
Analyzes and analyzes the frequency-domain analysis in paybybandwidth to determine the harmful EMI harmonic components in the signal.
Disadvantage: the blocking model still cannot be identified. When a blocking passive device exists, the simulation will fail. Due to latency
The time calculation method is unknown, and the timing constraints cannot be implemented currently.
Due to the time relationship, this article only describes the operation steps, the application must have a deep understanding of protel99se operations
The theoretical basis of force and signal integrity, as well as a certain understanding of the constraints-driven design methods of modern EDA software. As for yourself
Why does the company consider protel99se for signal integrity analysis?
Cadence
The problem of changing the design tool is that the company is not familiar with cadence to take care of others, so I don't think about it any more.
When the demand is high, the cadence may not be used, and it is required to change the design tool repeatedly and there is no result, so you have to play on protel99se
This is the origin of this article.