The metastable state in digital system and its solving methods

This article turns from http://www.cnblogs.com/linjie-swust/archive/2012/01/07/YWT.html

1. Application background 1.1 The cause of metastable occurrence

In the FPGA system, if the TSU and th of the trigger are not satisfied in the data transmission, or the release phase of the reset signal is dissatisfied with the recovery time of the effective clock edge (recovery times), the metastable state can be produced. At this time, the trigger output Q is in an indeterminate state for a long period after the effective clock edge, during which the Q end is in an oscillating state between 0 and 1, not equal to the value of data input d. This period of time is called the decision Time (resolution). After resolution time, the Q end will stabilize to 0 or 1, but stable to 0 or 1, is random, and the input does not necessarily have a relationship. 1.2 Metastable occurrence Occasions

As long as there are asynchronous components in the system, the metastable state is unavoidable, and the metastable state mainly occurs in the common design such as asynchronous signal detection, signal transmission in the cross-clock domain and reset circuit. 1.3 Metastable State Hazards

Due to the metastable state, the output of the Q end of the register may be a glitch, oscillation, fixed voltage value before it stabilizes. The generation of metastable in the signal transmission will lead to other digital components associated with it to make different judgments, some judgment to "1" some judgment to "0", some also into the metastable, digital components will be logical confusion. Having a metastable state in the reset circuit may cause the reset to fail. How to reduce the probability of metastable occurrence becomes an important consideration in FPGA design. 2. Theoretical Analysis 2.1 metastable state in signal transmission

In the synchronous system, the input signal is always synchronized with the system clock, which can meet the timing requirements of the register, so the metastable state does not occur. Metastable problems usually occur in some cross-clock domain signal transmission and asynchronous signal acquisition.

They occur for the following reasons:

(1) In the cross-clock domain signal transmission, because the source register clock and the purpose register clock phase shift is unknown, so the source register data emit data, the data may reach the destination register of the asynchronous clock domain at any time, so the requirements of the TSU and th of the purpose register cannot be guaranteed;

(2) in the asynchronous signal acquisition, because the asynchronous signal can reach the destination register at any point in time, there is no guarantee to satisfy the requirements of the purpose register tsu and th;

When the data is changed in the tsu-th time window of the destination register, the metastable phenomenon may occur when the data settling time or the hold time is not satisfied. As shown in 3.1.

Figure 3.1 metastable generation

It is shown that when the metastable TCO time is generated there will be Tmet (decision time) Oscillation time period, when the oscillation ends back to the stable state of "0" or "1", this is random. Therefore, the subsequent circuit judgment will be affected. A metastable 2.2.1 Asynchronous reset circuit for 2.2 reset circuit

In the reset circuit design, the reset signal is basically asynchronous, commonly used asynchronous reset circuit Verilog described as follows:

Always @ (Posedge CLK or Negedge rst_n)

Begin

if (!rst_n) a <= 1 ' b0;

else a <= b;

End

The integrated reset circuit is shown in Model 3.2:

Figure 3.2 Asynchronous reset circuit model

3.3, resets the timing diagram for the reset circuit. If the undo time of the asynchronous reset signal is within the trecovery (recovery time) and tremoval (removal time), it is bound to cause the metastable generation, the output at the clock edge of the TCO will generate oscillation, the oscillation time is tmet (decision time), and finally stabilized to "0" or "1", May cause the reset to fail.

Fig. 3.3 The metastable state of synchronous reset circuit of asynchronous reset sequential 2.2.2

In the reset circuit, because the reset signal is asynchronous, so some design uses synchronous reset circuit to reset, and most of the data for the synchronous reset circuit is not considered to occur metastable, in fact, synchronous circuit will also occur metastable, but the probability is less than the asynchronous reset circuit.

The following Verilog code describes the synchronous reset circuit.

Always @ (Posedge CLK)

Begin

if (!rst_n) a <= 1 ' b0;

else a <= b;

End

Integrated out of hardware circuit 3.4 is shown.

Figure 3.4 Synchronous Reset Circuit

In this case, we do not discuss the problem of the resource consumption of synchronous reset, but only the metastable generation of synchronous reset is discussed.

When the input din is high, and the undo time of the reset signal is within the TSU and th of CLK, the metastable state is subsequently generated. 3.5 Timing is shown, when the reset time in CLK tsu and th, the input data is "1", through and input data and after the data is also in the CLK tsu and th, so it is bound to cause similar to the asynchronous signal acquisition of metastable conditions.

Fig. 3.5 Timing diagram of synchronous reset circuit 2.3 The probability of metastable generation and crosstalk probability

In the actual FPGA circuit design, it is often thought how to reduce the effect of metastable on the system, few people consider how to reduce the probability of metastable occurrence, as well as the probabilistic problem of metastable crosstalk. Occurrence probability of metastable 2.3.1

It is found from the above that the metastable state of the system occurs because the TSU and th of CLK are not satisfied, or the removal and recovery time of the reset signal is not satisfied. The tsu+th of commonly used FPGA devices is approximately equal to 1ns, and the complex displacement addition and recovery time are approximately equal to 1ns.

When the asynchronous signal is not a set of data, or a small amount of signal, it is necessary to synchronize the asynchronous signal, such as the acquisition of an asynchronous pulse signal, as long as the pulse signal changes occur in the clock tsu and th window, it is likely to produce metastable, metastable generation probability is:

Probability = (Settling time + hold time)/acquisition clock period (equation 3-1)

As can be seen from Equation 3-1, the probability of metastable occurrence increases with the increase of CLK frequency.

For example, for the system to use a 100M clock to capture an external signal, the acquisition clock period of 10ns, the acquisition of the probability of metastable: 1ns/10ns = 10%

Similarly, using a 300M clock to capture an external signal, the probability of the metastable is: 1ns/3.3ns = 30%

If an external signal is collected using a clock with a three-phase phase difference of 120°, the probability of metastable is close to 90%.

Therefore, in the process of asynchronous signal acquisition, we want to reduce the probability of metastable occurrence:

(1) Reduce the system working clock, increase the system cycle, the metastable probability will be reduced;

(2) The use of better technology FPGA, that is, tsu and th time of the small FPGA device; the crosstalk probability of 2.3.2 metastable

When using asynchronous signal to use, good design will be synchronous processing of asynchronous signals, synchronization is generally used multilevel D trigger cascade processing, 3.6, using the three-level D trigger to synchronize asynchronous signals.

Figure 3.6 Level Three register synchronization

Most of the data of this model is that the first stage register to produce the metastable state, the second stage register stable output probability is 90%, the third pole register stable output probability is 99%, if the metastable follow the circuit has been passed down, it will be a weak self-repairing system directly collapse. Next we analyze the probability of this crosstalk.

3.7 shows a normal first level register with metastable, second-and third-pole registers to eliminate the metastable time series model.

Figure 3.7 Level Three register de-metastable

As can be seen, when the first register is metastable, after the oscillation of the Tmet stabilized, the second level register can collect a stable value. But why is the second-level register still likely to produce metastable state?

Because the oscillation time Tmet is affected by many factors, so the tmet time is long and short, so when the tmet time is longer than a collection period, then the second level register will be collected to metastable. As shown in 3.8.

Figure 3.8 Level Two register metastable

It is known that the second stage is also a metastable state, so in this case, the metastable generation Crosstalk, from the first level register to the second register, also may be from the second level register to Crosstalk to the third level register. This will make the design logic error, resulting in metastable transmission, may cause the system to crash. 2.3.3 Metastable Oscillation Time Tmet

The Tmet of metastable oscillation time is related to the acquisition stability of the post-level registers, and the Tmet influence factors include: the production process, temperature, environment and the time of register acquisition to metastable state. Even certain conditions, such as interference and radiation, can cause tmet growth. 3. Application Analysis

With metastable state, we need to eliminate the metastable state, there are three ways to eliminate metastable state:

(1) synchronous processing of asynchronous signals;

(2) using FIFO to buffer the cross-clock domain data communication;

(3) The Reset circuit adopts asynchronous reset, synchronous release mode processing. 3.1.1 Synchronous extraction of an asynchronous signal edge

In asynchronous communication or cross-clock domain communication process, the most common is to asynchronous signal synchronous extraction edge processing. Extracting the rising edge of an asynchronous signal is usually shown in Listing 4.1 of the program.

Program Listing 4.1 Bipolar Register Extraction Edge

Input Sig_nsyn;

Wire sig_nsyn_p;

REG[1:0] Sig_nsyn_r;

Always @ (Posedge CLK or Negedge rst_n)

Begin

if (!rst_n) Sig_nsyn_r <= 2 ' D0;

else Sig_nsyn_r <= {sig_nsyn_r [0], Sig_nsyn};

End

Assign sig_nsyn_p = sig_nsyn_r[0] & ~sig_nsyn_r[1];

This edge extraction method is not suitable for a stable system, for example: When the first level register to the metastable state, which will inevitably cause sig_nsyn_p output metastable, so that the use of sig_nsyn_p signal to judge the circuit to determine the impact, and even determine the wrong value.

According to the metastable generation probability of the 3.3.1 subsection, if the probability of metastable is about 10% when the first register is planted at 100M, the probability of metastable will rise with the increase of system acquisition frequency. Therefore, in the asynchronous signal cross-band extraction edge, the general use of a multi-level register to eliminate the metastable, may be high system stability requirements, the use of more level register to eliminate the metastable, as shown in Listing 4.2, that is, the use of 4-level register to eliminate the metastable state, The corresponding edge signal is generated at a time of two clock cycles.

Listing 4.2 Multilevel registers extracting edge signals

Input Sig_nsyn;

Wire sig_nsyn_p;

REG[3:0] Sig_nsyn_r;

Always @ (Posedge CLK or Negedge rst_n)

Begin

if (!rst_n) Sig_nsyn_r <= 2 ' D0;

else Sig_nsyn_r <= {Sig_nsyn_r [2::0], Sig_nsyn};

End

Assign sig_nsyn_p = sig_nsyn_r[2] & ~sig_nsyn_r[3]; 3.1.2 FIFO for asynchronous cross-frequency data processing

When the data flow from one clock domain to another clock domain, in most cases, the FIFO is used as the intermediate buffer, and the double clock is used to buffer the data, which can avoid the occurrence of metastable state. 3.1.3 Asynchronous reset, synchronous release

For the metastable state in the reset situation, it is often due to the recovery time and the removal clock is not satisfied, so the most commonly used processing method is to use asynchronous reset, synchronous release. Common circuit models are shown in. The second level register output is used as the global reset signal output.

Program listing 4.3 Asynchronous reset processing

Wire sys_rst_n;

reg [1:0] rst_r;

Always @ (Posedge CLK or Negedge rst_n)

Begin

if (!rst_n) Rst_r <= 2 ' D0;

else Rst_r <= {rst_r[0], 1 ' B1};

End

Assign sys_rst_n = rst_r[1];

The above three ways to deal with asynchronous signals, asynchronous data, and asynchronous reset can effectively improve the stability of the system. Reduce the production of metastable state.

The metastable state in digital system and its solving methods