The question of the interruption of the "you have to let the dead minister die, not to die, not to die" on the niosii 9.1 SP1

I am dying. I am dying. I am so sad...

Because the camera is tuned, one of the modes is "FPS switching", which requires the use of PIO external interruptions, but it has never been written before. It should be quite simple to use 51 in the past. As a result, it almost gave me the urge to die...

FuckingCodeInterrupted InitializationOver there, I tried to suppress the urge to die again and again.

First of all, the nios91 with enhanced interrupt, of course this is not the key to the problem, I do not detail, see the teeth of the blog: http://www.cnblogs.com/yuphone/archive/2010/05/13/1734712.html

The debug program is interrupted n times to view details, but I really want to smash the computer. The following is the prototype of alt_ic_arq_register () and the internal int alt_irq_register. I don't know why this is called enhanced mode, I heard that this is to facilitate future upgrades:

Int alt_ic_isr_register(Alt_u32 ic_id, alt_u32 IRQ, alt_isr_func ISR,
Void * isr_context, void * flags)
{
Return alt_irq_register (IRQ, isr_context, ISR );
}

Int alt_irq_register(Alt_u32 ID,
Void * context,
Alt_isr_func handler)
{
Int rc =-einval;
Alt_irq_context status;

If (ID <alt_nirq)
{
/*
* Interrupts are disabled while the handler tables are updated to ensure
* That an interrupt doesn' t occur while the tables are in an inconsistant
* State.
*/

Status = alt_irq_disable_all ();

Alt_irq [ID]. Handler = handler;
Alt_irq [ID]. Context = context;

Rc = (handler )? Alt_irq_enable (ID): alt_irq_disable (ID );

Alt_irq_enable_all (Status );
}
Return RC;
}

With the help of heroes in the group, nnd is not enough... In collaboration with the teeth and O my God, it still doesn't work... Dizzy

Finally, I accidentally tried to see if there were multiple ways to solve the problem. Then I went back to the system and found that I just forgot to choose enable bit_clearing... That's all.

Faint, knowing it, not knowing why, looking for the answer to the question !!! Why ??? Mentoring and mentoring solved the problem for N long and finally solved the problem of master a year ago. Now I am most miserable: it is the fault caused by eanbel bit_clearing:

 

It means:

Bit n in the edge capture register, if the input is captured (corresponding rising edge, falling edge), the corresponding bit is set to 1. A sister-in-law can read the edge capture register to determine the edge changes that occur on the PIO pin. If the "enable bit_clearing for edge capture register" option is disabled, writing any value to the edge capture register will clear all registers. Conversely, writing a special bit from 1 to a register will make edge capture ineffective.

According to my actual test, some of the above theories are verified.

(1) Enable bit_clearing:

The iowr_altera_avalon_pio_edge_cap (key_data_base, 0x03) is cleared because the problem is solved successfully.

(2) When enable bit_clearing is disabled:

Because DS indicates that all edge capture registers will be cleared when any value is written, iowr_altera_avalon_pio_edge_cap (key_data_base, any vaule) can be used to clear edgecapture. In actual testing, "Trim (key_data_base, 0x00); "and" iowr_altera_avalon_pio_edge_cap (key_data_base, 0x03); ", all achieved results. Of course, we tend to use 0 for resetting, which leads to another misunderstanding.

But it is clear that all these can achieve the goal. Why is it so embarrassing for Altera ?? Is it necessary ???

According to my master's explanation, the explanation is as follows:

(1) In general, external interruptions will not be achieved at the same time, So bit_clearing seems meaningless. For example, if we capture the button, press the button to make the LED shine, and press it to make it shine at the same time, there is no problem with this. Direct iowr_altera_avalon_pio_data (led_data_base, edge_capture); well !!!

(2) but this does not reject the interruption of synchronization capture. When synchronous capture is interrupted, bit_clearing can be used to work, which may be more flexible. When the interrupt is reached at the same time, Pio can certainly capture two interrupt signals at the same time, but the execution in the main () function is very embarrassing at this time. Who exactly listens to the two interruptions? (One of your parents asked you to cook for him, the other one asked you to play chess with him. What the fuck do I listen to? I quit and continue playing nios2 !)

This is equivalent to the Asynchronous Method in OpenGL. It is OK only after synchronous processing ). Therefore, bit_clearing is used to block the bit that captures the interrupt at the same time, and the other is blocked next time to allow the CPU to execute commands, giving the CPU a chance to hear who it should be, this can also effectively prevent the CPU from being crashed (TMD Lao Tzu quit ).

Because the pio irs assigns an IRQ in the system, it does not matter the single chip microcomputer's "interrupt priority" statement. Therefore, bit_clearing can only be used to perfectly allocate CPU tasks.

 

The above description basically explains that the zlg translation below is wrong. I have also found otherErrorIt seems that the original dt is good!

Finally, I will explain why iowr_altera_avalon_pio_edge_cap (key_data_base, 0x00) crashes when enable bit_clearing is enabled,ProgramThe problem in Initialization is:

According to Altera's DT (I analyzed (2) above), when enable bit_cleraing is enabled, We need to write 1 to the corresponding bit to clear the flag bit. (Many people on the internet set the value 0, probably because they didn't enbale bit_clearing), but we gave the value 0 to identify edagcapture. In this way, the interrupt mark cannot be cleared, therefore, one death is in it (the so-called King let the minister die, the Minister has to die, not dead also have to die ). Only clear. According to my verification, write 1 to clear the corresponding bit, which can solve the problem well.

At the same time, I refuted my blog and tempted my fatal problem (of course, I am very grateful to myself, because his help for me is far better than the pain of the past two days, maybe someone else NC error haha): Enable bit_clearing opened, while clearing the edge register but gave 0: http://www.cnblogs.com/yuphone/archive/2010/11/25/1887621.html

.

Now the problem is quite clear. I thought that Altera had a mental illness, and finally found that it was not a software problem or an ALTERA mental disorder, but that we didn't take DS seriously.

"Altara is otra, a younger brother of Altman. Moto is a Motorola, and a motorcycle also needs to be pulled by a hacker .."(Master is really a god !!!) Therefore, we can't keep complaining about Altera. What they do is generally based on a brother.

Paste the code below:

In general, no matter how you configure enable bit_clearing, it will never be wrong to clear 1 !!!

/*
* Sys_main.c
*
* Created on: 2011-4-1
* Author: crazybingo
*/

# Include <stdio. h>
# Include "unistd. H"
# Include "system. H"
# Include "alt_types.h"
# Include "sys/alt_irq.h"
// # Include "Io. H"
# Include "altera_avalon_pio_regs.h"

// # Include "../INC/my_sopc.h"
// # Include "../INC/key_scan.h"

Void key_interrupts (void * key_isr_context );
Void key_interrupts_init (void );

// Define global variables to store edge capture values
Volatile int edge_capture;

Int main (void)
{
Key_interrupts_init ();

While (1)
{
Iowr_altera_avalon_pio_data (led_data_base, edge_capture );
}
Return 0;
}

// * Key interrupt initialization */
Void key_interrupts_init (void)
{
/** // * Recast the edge_capture pointer to match the alt_irq_register () function
* Prototype .*/
Void * edge_capture_ptr = (void *) & edge_capture;
/** // * Enable all 2 button interrupts .*/
Iowr_altera_avalon_pio_irq_mask (key_data_base, 0x03 );
/** // * Reset the edge capture register. Enable bit_clearing turn0 off, write any vaule will take effect */
Iowr_altera_avalon_pio_edge_cap (key_data_base, 0x03); // active high always take effect
/** // * Register the interrupt handler .*/
Alt_ic_isr_register
(
Key_data_irq_interrupt_controller_id, // Number of the interrupt controller, copied from system. h
Key_data_irq, // hardware interrupt number, copied from system. h
Key_interrupts, // interrupt service subfunction
Edge_capture_ptr, // point to the data structure related to the device driver instance
Null // flags, reserved for unused
);
}

// Press the key to interrupt the Service Program (Interrupt Service routime), and every time the descent edge enters the interrupted execution
Void key_interrupts (void * key_isr_context)
{
/** // * Cast context to edge_capture's type. It is important that this be
* Declared volatile to avoid unwanted Compiler optimization.
*/
Volatile int * edge_capture_ptr = (volatile int *) key_isr_context;
/** // * Store the value in the button's edge capture register in * context .*/
* Edge_capture_ptr = iord_altera_avalon_pio_edge_cap (key_data_base );
/** // * Reset the edge capture register .*/
Iowr_altera_avalon_pio_edge_cap (key_data_base, 0x03 );
}

Finally, I can proceed to the next step... Liu Yinghua-sometimes, solving the problem is more painful than solving how to do it, but at this time it solved the mistakes of the master and the teeth. At the same time, I can finally relax, because of this interruption, thanks to cyclone iii pcb, I was almost over, but finally solved the problem, tired and happy.

Listen to master, go on!

 

Appendix:

Http://www.cnblogs.com/yuphone/archive/2010/05/13/1734712.html

Http://www.cnblogs.com/nick123/archive/2009/05/07/1451975.html

Http://www.cnblogs.com/yuphone/archive/2010/11/25/1887621.html